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AS3524 Datasheet(PDF) 28 Page - ams AG |
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AS3524 Datasheet(HTML) 28 Page - ams AG |
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28 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 28 - 124 5.2.7 USB 2.0 HS OTG interface The USB 2.0 on-chip interface includes the USB 2.0 On-The-Go Physical Interface and the HS OTG controller. Figure 10 USB 2.0 Interface 5.2.7.1 HS OTG controller subsystem The Synopsys HS OTG subsystem is a configurable design. The HS OTG subsystem is fully compliant with the On-The- Go supplement to the USB 2.0 specification, Revision 1.0a. The subsystem supports high speed (480-Mbps) and full- speed transfers. It is designed to interface to the AMBA AHB bus, shielding the application from the complexities of the HS OTG subsystem-native protocols and simplifying the system interface. The OTG subsystem can be configured using application software as follows: • OTG dual-role device (DRD) • USB High-Speed (HS) device • OTG device only • USB HS mini host • OTG mini host only • USB Full-Speed (FS) device The HS OTG subsystem has the following interfaces • the UTMI+, which connect the on-chip PHY to the HS OTG core • the AHB slave interface, which provides the microcontroller with read and write access to the core's control and status register (CSRs) • the AHB master interface, which enables the core to act as a master on the AHB to transfer data to and from the core's DMA controller • the descriptor prefetch buffer RAM interface, which connects to an single-port RAM for DMA descriptor prefetch buffer storage • the data RAM interface, which connects to and dual-port RAM (FIFO memory) for transaction data storage General features • handles all clock synchronisation within the core • includes built-in DMA • uses a descriptor prefetch buffer for optimal AHB use in host mode • includes hardware transaction scheduling for enhanced performance • supports adaptive buffering for dynamic FIFO memory allocation, avoiding gaps in RAM utilisation • supports memory mapped address space for the CSRs • SOFs are supported in high/full speed modes USB 2.0 supported features • supports up to 15 configurations in Device mode • each configuration supports 15 interfaces • each interface handles up to 15 alternate settings recovers clock and data from the USB • supports session request protocol (SRP) • supports a generic root hub • supports session request protocol (SRP) • includes auto ping/split completion capabilities • supports Host Negotiation Protocol (HNP) • complies with UTMI+ level 3 interface Implemented Controller configurations are: • configured with 4 host channels and 3 bidirectional- plus 1 in-endpoints in device mode • dynamic alternate configuration selection (for different bandwidths of isochronous endpoints) |
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