AS3524 datasheet(78/124 Pages) AMSCO

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AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

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clock domain crossing: the FiFo is at the boarder of clock domain PCLK and DBOPCLK. All necessary synchronisation is done internally. All

flags are available as push flags (synchronised to the push clock PCLK) and pop flags (synchronised to the POP clk, which is synchronous to

DBOPCLK.

The FiFo controller gives empty, almost empty, half full, almost full and full flags which are available in two fashions: synchronous to the push or the

pop side (pop_empty, push_empty, …).

5.3.12.3 Control Signal Generator

Four independent control signals can be generated: typical application for such signals is a 80xx interface with RS, RD*, WR* and E or a 68xx

interface with RS, E, RWN. The idea of this control signal generator is a general-purpose block, which generates any signal timing/waveform that is

necessary to transfer the data to any specific display.

Polarity Parameters

For each of the control signals c0 - c3 following polarity parameters are defined:

•

p0 … polarity 0 at start of cycle

•

p1 … polarity 1 following polarity 0

•

p2 … polarity 2 following polarity 1

Following figure shows an example for timing waveforms defined with these control parameters.

Figure 32 DBOP timing waveform

Tperiod

P0, P1, P2 = 000

P0, P1, P2 = 001

P0, P1, P2 = 010

P0, P1, P2 = 011

P0, P1, P2 = 100

P0, P1, P2 = 101

P0, P1, P2 = 110

P0, P1, P2 = 111

Static 0

NRZ 1

RZ 1

NRZ 1

RZ 1

Static 1

RO 1

Quiescent State

The control signals are only generated with each data output cycle (data output cycles are generated as long as the FiFo is not empty). With FiFo

empty and in the absence of a read cycle, all control signals are set to a quiescent state. For each control signal, this quiescent state can be

programmed either to 1 or 0.

AS3524 Datasheet(PDF) 78 Page - ams AG

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