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AS3524 Datasheet(PDF) 62 Page - ams AG |
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AS3524 Datasheet(HTML) 62 Page - ams AG |
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62 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 62 - 124 5.3.11 NAND Flash Interface The NAND FLASH interface module enables control of NAND flash devices. The design follows the hardware reference implementation described in SMIL (SmartMediaTM Interface Library), Hardware Edition 1.00, TOSHIBA Corporation, but has extensions to support the latest generation of NAND flash devices. Programming and Reading can be done either by direct access to/from data register (normal mode) or by using a FIFO (burst mode). NAF supports 8-bit and 16-bit transfers. Features • interface compliant to AMBA APB bus • generation of interrupt request signal with several maskable interrupt sources (ready, empty, almost_empty…) • hardware error detection (2 detect, 1 correct per 256 bytes block) for up to 8 *256 bytes (up to 24 ECC bytes) • 8-bit and 16-bit transfer Mode fore X8/X16 devices • big endian / little endian support • DMA Mode • Normal Mode • Data/Mode/Status Register • write/read on/from data register automatically generates read/write strobes • Burst Transfer • 36 x 32 bit FIFO for DMA/burst support • read- & write controller for automatic data resizing (32bit <=> 8/16bit) and read/write control • configurable strobe (low and high time) for higher PCLK clocks / lower speed NAND Flash devices • little endian/ big endian selectable • load interrupts when FIFO is ‘almost_empty’ & ’almost_full’ to ensure continuous data flow Figure 29 Block Diagram of NAND Flash Interface |
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