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AS3524 Datasheet(PDF) 86 Page - ams AG

Part # AS3524
Description  Advanced Audio Processor System
PDF  124 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS3524 Datasheet(HTML) 86 Page - ams AG

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AS3524 C21 / C22
austriamicrosystems
Data Sheet, Confidential
© 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1.11
86
- 124
Table 64 UART Clock divider lower byte register
Name
Base
Default
UART_DLO_REG
AS3525_UART_BASE
0xC8110000
Clock divider lower byte register
Offset: 0x00
DLS set to 1
This register holds the clock divider value (decimal) which is used to derive the baud
clock. To achieve a desired baud rate, the baud clock should be 16-times higher then
the baud rate. To derive this clock the ratio of the system clock and the required baud
clock should be calculated and the value should be programmed into the clock divider
lower byte and higher byte registers (UART_DLO_REG and UART_DHI_REG).
Clock divider value = (input frequency) / (baud rate x 16)
Bit
Bit Name
Default
Access
Bit Description
7:0
UART_DLO_REG
00000000
W
This register holds the lower byte of the decimal divisor value
to calculate baud clock.
Table 65 UART Clock divider higher byte register
Name
Base
Default
UART_DHI_REG
AS3525_UART_BASE
0xC8110000
Clock divider higher byte register
Offset: 0x04
DLS set to 1
This register holds the higher byte of the decimal divisor value to calculate baud clock.
Bit
Bit Name
Default
Access
Bit Description
7:0
UART_DHI_REG
00000000
W
This register holds the higher byte of the decimal divisor value
to calculate baud clock.
Table 66 UART Interrupt enable register
Name
Base
Default
UART_INTEN_REG
AS3525_UART_BASE
0xC8110000
Interrupt enable register
Offset: 0x04
DLS set to 0
This register will enable the three types of interrupts. Setting the bits of this register to
logic 1 enables the selected interrupt.
Bit
Bit Name
Default
Access
Bit Description
7:3
Reserved
00000
These bits are reserved for future use.
2
lnStatusEn
0
W
This bit enables the “rxLineStatus” interrupt.
1
txDataEmptyEn
0
W
This bit enables the “txDataEmpty” interrupt.
0
rxDataRdyEn
0
W
This bit enables the “rxDataRdy” interrupt.



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