AS3524 datasheet(53/124 Pages) AMSCO

53 / 124 page

AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

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Revision 1.11

- 124

5.3.8.2 I2S Input Signals

The following specifications signals are given:

•

Data are valid at rising/falling edge of SCLK (depending on I2SI_CONTROL’s setting).

•

The left and right channels are indicated by the LRCK signal.

The timing diagram of the standard I2S interface signals from the ADC is shown below (Figure 27).

Figure 24 - I2S standard timing diagram

Left Channel

Right Channel

LRCK

SCLK

SDATA

24 bit

period(fsaudio) / 2

While the I2S standard states that the LRCK line changes one clock cycle before the MSB is transmitted. If the ADC sends the MSB directly after

LRCK line changes, the SDATA_valid bit in the I2SI_CONTROL register must be set.

Figure 25 - I2S standard timing diagram with SDATA valid directly after LRC changes

Left Channel

Right Channel

LRCK

SCLK

SDATA

24 bit

period(fsaudio) / 2

Assumption: The LRCK toggles every 32 clocks of SCLK.

5.3.8.3 Power Modes

The I2SINIF contains two clock domains. The PCLK domain can be turned off in the clock controller. The SCLK clock domain can be turned off

locally using the SCLK_idle bit in the I2SIN_CONTROL register. Note that the SCLK’s clock gating signal has to be synchronized with the SCLK

clock in order to guarantee correct operation.

If PCLK is turned off, no interrupt must be triggered by the I2SINIF module.

The I2SI_MCLK clock can be turned on/off in the clock generation unit.

5.3.8.4 Loopback Feature

On the AS3525 are two I2S interfaces:

I2SOUTIF is responsible to send values to the DAC of the audio chip via I2SO_SDATA

I2SINIF is responsible to receive audio values from ADC of the audio chip via I2SI_SDATA

In the AS3525 both SDATA signals are provided as loopback signals (I2SO_FSDATA, I2SI_FSDATA):

I2SO_SDATA to I2SINIF: This loopback is mainly for testing the transmit and receive paths of both I2S

interfaces. The loopback signal is called I2SO_FSDATA.

I2SI_SDATA to I2SOUTIF: This loopback feature allows the application to echo the input audio samples directly

to a loudspeaker. The signal provided by the I2SINIF is called I2SI_FSDATA.

In normal mode the I2SINIF pushes audio values into the FIFO based on the I2SI_SDATA signal. If the loopback feature is enabled, the

sdata_source bit in the control register must be set to 3. The FIFO content is filled with audio values send by the I2SOUTIF (signal I2SO_FSDATA).

NOTE: This feature will only be available if SCLK is the same for I2S input and output interface. For implementation the I2SO_FSDATA signal is

simply routed through a multiplexer to the I2SI_SDATA interface.

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