AS3524 datasheet(77/124 Pages) AMSCO

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AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

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Revision 1.11

- 124

Dbop Integration Test Registers

The Dbop module is programmed to integration test mode using test control register. The integration test mode enables the user to access all the

input/output pins through the APB bus interface.

Name

Offset

R/W

Reset Value

Description

DBOPITC

0x18

R/W

0x00000000

DBOP integration test control register

DBOPITIP1

0x1C

R/W

0x00

DBOP integration test input register

DBOPITOP1

0x20

0x0

DBOP integration test output register

Table 58 DBOPITC test register

bits

Name

type

function

default

value

31:1

reserved

iten

r/w

Integration test enable

1 will enable the integration test

mode

Table 59 DBOPITIP1 test register

bits

Name

type

function

default

value

31:5

reserved

Testctrloen

r/w

Test value for

out_enControl_n

The value on this bit will be

reflected in out_enControl_n

Testdataoen

r/w

Test value for

out_enData_n

The value on this bit will be

reflected in out_enData_n

Testdmasreq

r/w

Test value for DMASREQ

The value on this bit will be

reflected in

DBOPDMACSREQ

Testdmabreq

r/w

Test value for DMABREQ

The value on this bit will be

reflected in

DBOPDMACBREQ

testirq

r/w

Test value for interrupt

The value on this bit will be

reflected in DBOPIRQ

Table 60 DBOPITOP1 test register

bits

Name

type

function

default

value

31:1

reserved

Testdmaclr

DBOPDMACCLR test

Read of this register will return the

value on the

DBOPDMACCLR input.

5.3.12.2 DBOP DMA Interface

This block generates all necessary interface signals with the DMAC primecell for DMA transfer. Following table gives a description of these signals.

DBOPDMASREQ

single word request, asserted by DBOP. This signal is asserted when there is at least one

empty location in the FiFo

DBOPDMABREQ

burst DMA transfer request, asserted by DBOP. This signal is asserted when there are at

least four empty locations in the FiFo

DBOPDMACLR

DMA request clear, asserted by DMA controller to clear the DMA request signals. If DMA

burst transfer is requested, the clear signal is asserted during the transfer of the last data

in the burst

Symmetric FiFo

The FiFo buffer has two main purposes:

•

data buffering: the FiFo contains 128 locations with 32 bits for data storage: with according DMA transfer, the data can be transferred in short

time without need for any SW control

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