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82G33 Datasheet(PDF) 67 Page - Intel Corporation

Part # 82G33
Description  Graphics and Memory Controller Hub
PDF  437 Pages
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Manufacturer  INTEL [Intel Corporation]
Direct Link  http://www.intel.com
Logo INTEL - Intel Corporation

82G33 Datasheet(HTML) 67 Page - Intel Corporation

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System Address Map
Datasheet
67
3.7
Graphics Memory Address Ranges (Intel® 82Q35,
82Q33, and 82G33 (G)MCH Only)
The (G)MCH can be programmed to direct memory accesses to IGD when addresses
are within any of five ranges specified via registers in (G)MCH’s Device 2 configuration
space.
• The Memory Map Base Register (MMADR) is used to access graphics control
registers.
• The Graphics Memory Aperture Base Register (GMADR) is used to access graphics
memory allocated via the graphics translation table.
• The Graphics Translation Table Base Register (GTTADR) is used to access the
translation table.
These ranges can reside above the Top-of-Low-DRAM and below High BIOS and APIC
address ranges. They MUST reside above the top of memory (TOLUD) and below 4 GB
so they do not steal any physical DRAM memory space.
GMADR is a Prefetchable range in order to apply USWC attribute (from the processor
point of view) to that range. The USWC attribute is used by the processor for write
combining.
3.8
System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SMM
RAM). The (G)MCH supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG),
and Top of Memory Segment (TSEG). System Management RAM space provides a
memory area that is available for the SMI handlers and code and data storage. This
memory resource is normally hidden from the system OS so that the processor has
immediate access to this memory space upon entry to SMM. The (G)MCH provides
three SMRAM options:
• Below 1 MB option that supports compatible SMI handlers.
• Above 1 MB option that allows new SMI handlers to execute with write-back
cacheable SMRAM.
• Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. For the 82Q35/82Q33/82G33,
the TSEG area lies below IGD stolen memory.
The above 1 MB solutions require changes to compatible SMRAM handlers code to
properly execute above 1 MB.
Note: DMI Interface and PCI Express masters are not allowed to access the SMM space.



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