82G33 datasheet(76/437 Pages) INTEL

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(G)MCH Register Description

Datasheet

4.2

Configuration Process and Registers

4.2.1

Platform Configuration Structure

The DMI physically connects the (G)MCH and the Intel ICH9; so, from a configuration

standpoint, the DMI is logically PCI bus 0. As a result, all devices internal to the

(G)MCH and the Intel ICH9 appear to be on PCI bus 0.

Note: The ICH9 internal LAN controller does not appear on bus 0 – it appears on the

external PCI bus (whose number is configurable).

The system’s primary PCI expansion bus is physically attached to the Intel ICH9 and,

from a configuration perspective, appears to be a hierarchical PCI bus behind a PCI-

to-PCI bridge and therefore has a programmable PCI Bus number. The PCI Express

Graphics Attach appears to system software to be a real PCI bus behind a PCI-to-PCI

bridge that is a device resident on PCI bus 0.

Note: A physical PCI bus 0 does not exist and that DMI and the internal devices in the

(G)MCH and Intel ICH9 logically constitute PCI Bus 0 to configuration software.

The (G)MCH contains four PCI devices within a single physical component. The

configuration registers for the four devices are mapped as devices residing on PCI bus

• Device 0: Host Bridge/DRAM Controller. Logically this appears as a PCI device

residing on PCI bus #0. Device 0 contains the standard PCI header registers, PCI

Express base address register, DRAM control (including thermal/throttling

control), configuration for the DMI, and other (G)MCH specific registers.

• Device 1: Host-PCI Express Bridge. Logically this appears as a “virtual” PCI-to-

PCI bridge residing on PCI bus #0 and is compliant with PCI Express Specification

rev 1.0. Device 1 contains the standard PCI-to-PCI bridge registers and the

standard PCI Express/PCI configuration registers (including the PCI Express

memory address mapping). It also contains

Isochronous and Virtual Channel

controls in the PCI Express extended configuration space.

• Device 2: Internal Graphics Control (82Q35, 82Q33 ,82G33 GMCH only).

Logically, this appears as a PCI device residing on PCI bus #0. Physically, device 2

contains the configuration registers for 3D, 2D, and display functions.

• Device 3: Manageability Engine Device. ME Control.

82G33 Datasheet(PDF) 76 Page - Intel Corporation