82G33 datasheet(10/437 Pages) INTEL

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Datasheet

9.2.14

MLAT— Maximum Latency ...................................................... 310

9.2.15

HFS— Host Firmware Status ................................................... 310

9.2.16

PID— PCI Power Management Capability ID .............................. 310

9.2.17

PC— PCI Power Management Capabilities.................................. 311

9.2.18

PMCS— PCI Power Management Control And Status ................... 312

9.2.19

MID— Message Signaled Interrupt Identifiers ............................ 313

9.2.20

MC— Message Signaled Interrupt Message Control ..................... 313

9.2.21

MA— Message Signaled Interrupt Message Address .................... 314

9.2.22

MUA— Message Signaled Interrupt Upper Address (Optional)....... 314

9.2.23

MD— Message Signaled Interrupt Message Data ........................ 315

9.2.24

HIDM—HECI Interrupt Delivery Mode ....................................... 315

9.3

IDE Function for Remote Boot and Installations PT IDER Register

Details (D3:F2) (Intel® 82Q35 and 82Q33 GMCH Only)............................ 316

9.3.1

ID—Identification .................................................................. 317

9.3.2

CMD—Command Register ....................................................... 317

9.3.3

STS—Device Status ............................................................... 319

9.3.4

RID—Revision ID................................................................... 320

9.3.5

CC—Class Codes ................................................................... 320

9.3.6

CLS—Cache Line Size............................................................. 320

9.3.7

MLT—Master Latency Timer .................................................... 321

9.3.8

HTYPE—Header Type ............................................................. 321

9.3.9

PCMDBA—Primary Command Block IO Bar ................................ 322

9.3.10

PCTLBA—Primary Control Block Base Address............................ 322

9.3.11

SCMDBA—Secondary Command Block Base Address................... 323

9.3.12

SCTLBA—Secondary Control Block base Address ........................ 323

9.3.13

LBAR—Legacy Bus Master Base Address ................................... 324

9.3.14

SS—Sub System Identifiers .................................................... 325

9.3.15

EROM—Expansion ROM Base Address....................................... 325

9.3.16

CAP—Capabilities Pointer........................................................ 326

9.3.17

INTR—Interrupt Information ................................................... 326

9.3.18

MGNT—Minimum Grant .......................................................... 327

9.3.19

MLAT—Maximum Latency ....................................................... 327

9.3.20

PID—PCI Power Management Capability ID ............................... 327

9.3.21

PC—PCI Power Management Capabilities................................... 328

9.3.22

PMCS—PCI Power Management Control and Status .................... 328

9.3.23

MID—Message Signaled Interrupt Capability ID ......................... 330

9.3.24

MC—Message Signaled Interrupt Message Control ...................... 330

9.3.25

MA—Message Signaled Interrupt Message Address ..................... 331

9.3.26

MAU—Message Signaled Interrupt Message Upper Address .......... 331

9.3.27

MD—Message Signaled Interrupt Message Data ......................... 332

9.4

Serial Port for Remote Keyboard and Text KT Redirection Register

Details (D3:F3) (Intel® 82Q35 and 82Q33 GMCH Only)............................ 333

9.4.1

ID—Identification .................................................................. 334

9.4.2

CMD—Command Register ....................................................... 334

9.4.3

STS—Device Status ............................................................... 336

9.4.4

RID—Revision ID................................................................... 337

9.4.5

CC—Class Codes ................................................................... 337

9.4.6

CLS—Cache Line Size............................................................. 337

9.4.7

MLT—Master Latency Timer .................................................... 338

9.4.8

HTYPE—Header Type ............................................................. 338

9.4.9

KTIBA—KT IO Block Base Address............................................ 339

9.4.10

KTMBA—KT Memory Block Base Address................................... 339

9.4.11

SS—Sub System Identifiers .................................................... 340

9.4.12

EROM—Expansion ROM Base Address....................................... 341

9.4.13

CAP—Capabilities Pointer........................................................ 341

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