82G33 datasheet(75/437 Pages) INTEL

75 / 437 page

(G)MCH Register Description

Datasheet

Item

Definition

RW/K

Read / Write / Key bit(s). These bits can be read and written by software.

Additionally this bit, when set, prohibits some other bit field(s) from being

writeable (bit fields become Read Only).

RW/L

Read / Write / Lockable bit(s). These bits can be read and written by

software. Additionally there is a Key bit (which is marked R/W/K or R/W/L/K)

that, when set, prohibits this bit field from being writeable (bit field becomes

Read Only).

RW/L/K

Read / Write / Lockable / Key bit(s). These bits can be read and written by

software. Additionally this bit is a Key bit that, when set, prohibits this bit

field and/or some other specified bit fields from being writeable (bit fields

become Read Only).

RW/S

Read / Write / Sticky bit(s). These bits can be read and written by software.

Bits are not cleared by "warm" reset, but will be reset with a cold/complete

reset (for PCI Express related bits a cold reset is “Power Good Reset” as

defined in the PCI Express spec).

RW/S/B

Read / Write / Sticky / Blind bit(s). These bits can be read and written by

software. Additionally there is a selector bit which, when set, changes what

may be read from these bits. The value written is always stored in a hidden

read, some other status is read from this bit. When the selector bit indicates

that the written value should be read, the value in the hidden register is read

from this bit. Bits are not cleared by "warm" reset, but will be reset with a

cold/complete reset (for PCI Express related bits a cold reset is “Power Good

Reset” as defined in the PCI Express spec).

RW/SC

Read / Write / Self Clear bit(s). These bits can be read and written by

software. When the bit is ‘1’, hardware may clear the bit to ‘0’ based upon

internal events, possibly sooner than any subsequent software read could

retrieve a ‘1’.

RW/SC/L

Read / Write / Self Clear / Lockable bit(s). These bits can be read and

written by software. When the bit is ‘1’, hardware may clear the bit to ‘0’

based upon internal events, possibly sooner than any subsequent software

read could retrieve a ‘1’. Additionally there is a bit (which is marked R/W/K

or R/W/L/K) that, when set, prohibits this bit field from being writeable (bit

field becomes Read Only).

RWO

Write Once bit(s). Once written by software, bits with this attribute become

Read Only. These bits can only be cleared by a Reset. If there are multiple

R/WO fields within a DWORD, they should be written all at once (atomically)

to avoid capturing an incorrect value.

Write Only. These bits may be written by software, but will always return

zeros when read. They are used for write side-effects. Any data written to

these registers cannot be retrieved.

82G33 Datasheet(PDF) 75 Page - Intel Corporation

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