82G33 datasheet(60/437 Pages) INTEL

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System Address Map

Datasheet

3.2.1

ISA Hole (15 MB-16 MB)

A hole can be created at 15 MB – 16 MB as controlled by the fixed hole enable in

Device 0 space. Accesses within this hole are forwarded to the DMI Interface. The

range of physical DRAM memory disabled by opening the hole is not remapped to the

top of the memory – that physical DRAM space is not accessible. This 15 MB – 16 MB

hole is an optionally enabled ISA hole.

Video accelerators originally used this hole. It is also used by validation and customer

SV teams for some of their test cards. That is why it is being supported. There is no

inherent BIOS request for the 15 MB – 16 MB window.

3.2.2

TSEG

TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below IGD stolen memory,

which is at the top of Low Usable physical memory (TOLUD). SMM-mode processor

accesses to enabled TSEG access the physical DRAM at the same address. Non-

processor originated accesses are not allowed to SMM space. PCI Express, DMI, and

Internal Graphics originated cycle to enabled SMM space are handled as invalid cycle

type with reads and writes to location 0 and byte enables turned off for writes. When

the extended SMRAM space is enabled, processor accesses to the TSEG range without

SMM attribute or without WB attribute are also forwarded to memory as invalid

accesses (see table 8). Non-SMM-mode Write Back cycles that target TSEG space are

completed to DRAM for cache coherency. When SMM is enabled the maximum amount

of memory available to the system is equal to the amount of physical DRAM minus the

value in the TSEG register which is fixed at 1 MB, 2 MB, or 8 MB.

3.2.3

Pre-allocated Memory

Voids of physical addresses that are not accessible as general system memory and

reside within system memory address range (< TOLUD) are created for SMM-mode,

legacy VGA graphics compatibility, and GFX GTT stolen memory. It is the

responsibility of BIOS to properly initialize these regions. The following table

details the location and attributes of the regions. Enabling/Disabling these ranges are

described in the (G)MCH Control Register Device 0 (GCC).

Table 3-4. Pre-allocated Memory Example for 64 MB DRAM, 1 MB VGA, 1 MB GTT stolen

and 1 MB TSEG

Memory Segments

Attributes

Comments

0000_0000h –

03CF_FFFFh

R/W

Available System Memory 61 MB

03D0_0000h –

03DF_FFFFh

SMM Mode Only -

processor Reads

TSEG Address Range & Pre-allocated Memory

03E0_0000h –

03EF_FFFFh

R/W

Pre-allocated Graphics VGA memory.

1 MB (or 4/8/16/32/64/128/256 MB) when IGD

is enabled on the 82Q35/82Q33/82G33 GMCH.

03F0_0000h –

03FF_FFFFh

R/W

Pre-allocated Graphics GTT stolen memory.

1 MB (or 2 MB) when IGD is enabled on the

82Q35/82Q33/82G33 GMCH.

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