82G33 datasheet(25/437 Pages) INTEL

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Introduction

Datasheet

Term

Description

Media

Expansion

Card

(MEC)

Media Expansion Card. MEC provides digital display options for an Intel

Graphics Controller that supports MEC cards. Plugs into an x16 PCI Express

connector but uses the multiplexed SDVO interface. Adds Video In

capabilities to platform. Will not work with an Intel Graphics Controller that

supports DVO and ADD cards. MEC Will function as an ADD2 card in an

ADD2 supported system, but Video In capabilities will not work.

MCH

Memory Controller Hub. MCH is a component that contains the processor

interface, DRAM controller, and x16 PCI Express port (typically the external

graphics interface). It communicates with the I/O controller hub (Intel®

ICH9) over the DMI interconnect. The MCH does not contain an embedded

graphics controller.

MGAW

Maximum Guest Address Width. MGAW refers to the maximum DMA virtual

addressability supported by a DMA-remapping hardware implementation.

HAW

Host Address Width. This refers to the maximum host physical address that

can be accessed by a given processor / root-complex implementation. The

host BIOS typically reports the host system address map.

Host

This term is used synonymously with processor

HPA

Host Physical Address

IGD

Internal Graphics Device

INTx

An interrupt request signal where X stands for interrupts A, B, C and D

Intel® ICH9

Ninth generation I/O Controller Hub component that contains the primary

PCI interface, LPC interface, USB2.0, SATA, and other I/O functions. For this

GMCH, the term Intel® ICH refers to Intel® ICH9.

Intel® ME

Intel® Management Engine that provides core functionality for Intel® AMT.

IOTLB

I/O Translation Look aside Buffer. IOTLB refers to an address translation

cache in a DMA-remapping hardware unit that caches effective translations

from DVA (GPA) to HPA.

IOQ

In Order Queue

MVMM

A VMM offering that can be measured for security properties

MSI

Message Signaled Interrupt. A transaction conveying interrupt information to

the receiving agent through the same path that normally carries read and

write commands.

OOQ

Out of Order Queuing

PDE Cache/

Non-leaf

Cache

PDE (non-leaf) cache refers to address translation caches in a DMA-

remapping hardware unit that caches page directory entries at the various

page-directory levels. These are also referred to as non-leaf caches in this

document.

PCI Express*

A high-speed serial interface whose configuration is software compatible with

the legacy PCI specifications.

Primary PCI

The physical PCI bus that is driven directly by the Intel® ICH9 component.

Communication between Primary PCI and the (G)MCH occurs over DMI. Note

that the Primary PCI bus is not PCI Bus 0 from a configuration standpoint.

SERR

System Error. An indication that an unrecoverable error has occurred on an

I/O bus.

Rank

A unit of DRAM corresponding to eight x8 SDRAM devices in parallel or four

x16 SDRAM devices in parallel, ignoring ECC. These devices are usually, but

not always, mounted on a single side of a DIMM.

SCI

System Control Interrupt. Used in ACPI protocol.

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