82G33 datasheet(70/437 Pages) INTEL

70 / 437 page

System Address Map

Datasheet

3.8.7

SMM Access through GTT TLB (Intel® 82Q35, 82Q33,

82G33 GMCH Only)

Accesses through GTT TLB address translation to enabled SMM DRAM space are not

allowed. Writes will be routed to memory address 000C_0000h with byte enables de-

asserted and reads will be routed to memory address 000C_0000h. If a GTT TLB

translated address hits enabled SMM DRAM space, an error is recorded.

PCI Express and DMI Interface originated accesses are never allowed to access SMM

space directly or through the GTT TLB address translation. If a GTT TLB translated

address hits enabled SMM DRAM space, an error is recorded.

PCI Express and DMI Interface write accesses through GMADR range will be snooped.

Assesses to GMADR linear range (defined via fence registers) are supported. PCI

Express and DMI Interface tileY and tileX writes to GMADR are not supported. If, when

translated, the resulting physical address is to enabled SMM DRAM space, the request

will be remapped to address 000C_0000h with de-asserted byte enables.

PCI Express and DMI Interface read accesses to the GMADR range are not supported

therefore will have no address translation concerns. PCI Express and DMI Interface

reads to GMADR will be remapped to address 000C_0000h. The read will complete

with UR (unsupported request) completion status.

GTT fetches are always decoded (at fetch time) to ensure not in SMM (actually,

anything above base of TSEG or 640 KB – 1 MB). Thus, they will be invalid and go to

address 000C_0000h, but that is not specific to PCI Express or DMI; it applies to

processor or internal graphics engines. Also, since the GMADR snoop would not be

directly to the SMM space, there would not be a writeback to SMM. In fact, the

writeback would also be invalid (because it uses the same translation) and go to

address 000C_0000h.

3.9

Memory Shadowing

Any block of memory that can be designated as read-only or write-only can be

“shadowed” into (G)MCH DRAM memory. Typically this is done to allow ROM code to

execute more rapidly out of main DRAM. ROM is used as a read-only during the copy

process while DRAM at the same time is designated write-only. After copying, the

DRAM is designated read-only so that ROM is shadowed. Processor bus transactions

are routed accordingly.

3.10

I/O Address Space

The (G)MCH does not support the existence of any other I/O devices beside itself on

the processor bus. The (G)MCH generates either DMI Interface or PCI Express bus

cycles for all processor I/O accesses that it does not claim. Within the host bridge, the

(G)MCH contains two internal registers in the processor I/O space: Configuration

Address Register (CONFIG_ADDRESS) and the Configuration Data Register

(CONFIG_DATA). These locations are used to implement configuration space access

mechanism.

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