82G33 datasheet(37/437 Pages) INTEL

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Signal Description

Datasheet

Signal Name

Type

Description

FSB_DINVB_3:0

I/O

GTL+

Dynamic Bus Inversion: These signals are driven along with

the FSB_DB_63:0 signals. They indicate if the associated

signals are inverted. FSB_DINVB_3:0 are asserted such that

the number of data bits driven electrically low (low voltage)

within the corresponding 16 bit group never exceeds 8.

FSB_DINVB_x

Data Bits

FSB_DINVB_3

FSB_DB_63:48

FSB_DINVB_2

FSB_DB_47:32

FSB_DINVB_1

FSB_DB_31:16

FSB_DINVB_0

FSB_DB_15:0

FSB_DRDYB

I/O

GTL+

Data Ready: This signal is asserted for each cycle that data is

transferred.

FSB_AB_35:3

I/O

GTL+

Host Address Bus: FSB_AB_35:3 connect to the processor

address bus. During processor cycles, FSB_AB_35:3 are

inputs. The (G)MCH drives FSB_AB_35:3 during snoop cycles

on behalf of DMI and PCI-Express-G initiators. FSB_AB_35:3

are transferred at 2x rate. Note that the address is inverted on

the processor bus. The values stored in the POC register are

driven in these signals by the (G)MCH between PWROK

assertion and FSB_CPURSTB de-assertion to allow processor

configuration.

FSB_ADSTBB_1:0

I/O

GTL+

Host Address Strobe: The source synchronous strobes are

used to transfer FSB_AB_31:3 and FSB_REQB_4:0 at the 2x

transfer rate.

Strobe

Address Bits

FSB_ADSTBB_0

FSB_AB_16:3, FSB_REQB_4:0

FSB_ADSTBB_1

FSB_AB_31:17

FSB_DB_63:0

I/O

GTL+

Host Data: These signals are connected to the processor data

bus. Data on FSB_DB_63:0 is transferred at a 4x rate. Note

that the data signals may be inverted on the processor bus,

depending on the FSB_DINVB_3:0 signals.

82G33 Datasheet(PDF) 37 Page - Intel Corporation

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