82G33 datasheet(56/437 Pages) INTEL

56 / 437 page

System Address Map

Datasheet

3.1.1

DOS Range (0h – 9_FFFFh)

The DOS area is 640 KB (0000_0000h – 0009_FFFFh) in size and is always mapped to

the main memory controlled by the (G)MCH.

3.1.2

Legacy Video Area (A_0000h – B_FFFFh)

The legacy 128 KB VGA memory range, frame buffer, (000A_0000h – 000B_FFFFh)

can be mapped to IGD (Device 2), to PCI Express (Device 1), and/or to the DMI

Interface. The appropriate mapping depends on which devices are enabled and the

programming of the VGA steering bits. Based on the VGA steering bits, priority for

VGA mapping is constant. The (G)MCH always decodes internally mapped devices

first. Internal to the GMCH, decode precedence is always given to IGD. The (G)MCH

always positively decodes internally mapped devices, namely the IGD and PCI-

Express. Subsequent decoding of regions mapped to PCI Express or the DMI Interface

depends on the Legacy VGA configuration bits (VGA Enable and MDAP). This region is

also the default for SMM space.

Compatible SMRAM Address Range (A_0000h – B_FFFFh)

When compatible SMM space is enabled, SMM-mode processor accesses to this range

are routed to physical system DRAM at 000A 0000h – 000B FFFFh. Non-SMM-mode

processor accesses to this range are considered to be to the Video Buffer Area as

described above. PCI Express and DMI originated cycles to enabled SMM space are not

allowed and are considered to be to the Video Buffer Area if IGD is not enabled as the

VGA device. PCI Express and DMI initiated cycles are attempted as Peer cycles, and

will master abort on PCI if no external VGA device claims them.

Monochrome Adapter (MDA) Range (B_0000h – B_7FFFh)

Legacy support requires the ability to have a second graphics controller

(monochrome) in the system. Accesses in the standard VGA range are forwarded to

IGD, PCI Express, or the DMI Interface (depending on configuration bits). Since the

monochrome adapter may be mapped to anyone of these devices, the (G)MCH must

decode cycles in the MDA range (000B_0000h – 000B_7FFFh) and forward either to

IGD, PCI Express, or the DMI Interface. This capability is controlled by a VGA steering

bits and the legacy configuration bit (MDAP bit). In addition to the memory range

B0000h to B7FFFh, the (G)MCH decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh

and 3BFh and forwards them to the either IGD, PCI-Express, and/or the DMI

Interface.

PEG 16-bit VGA Decode

The PCI to PCI Bridge Architecture Specification Revision 1.2 requires that 16-bit VGA

decode be a feature.

82G33 Datasheet(PDF) 56 Page - Intel Corporation