82G33 datasheet(69/437 Pages) INTEL

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System Address Map

Datasheet

3.8.3

SMM Space Combinations

When High SMM is enabled (G_SMRAME=1 and H_SMRAM_EN=1) the Compatible

SMM space is effectively disabled. Processor-originated accesses to the Compatible

SMM space are forwarded to PCI Express if VGAEN=1 (also depends on MDAP);

otherwise, they are forwarded to the DMI Interface. PCI Express and DMI Interface

originated accesses are never allowed to access SMM space.

Table 3-6. SMM Space

Global Enable

G_SMRAME

High Enable

H_SMRAM_EN

TSEG Enable

TSEG_EN

Compatible

High (H)

Range

TSEG (T)

Range

Disable

Enable

Disable

Enable

Disable

Enable

Disabled

Enable

Disable

Disabled

Enable

3.8.4

SMM Control Combinations

The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit

allows software to write to the SMM ranges without being in SMM mode. BIOS

software can use this bit to initialize SMM code at powerup. The D_LCK bit limits the

SMM range access to only SMM mode accesses. The D_CLS bit causes SMM (both

CSEG and TSEG) data accesses to be forwarded to the DMI Interface or PCI Express.

The SMM software can use this bit to write to video memory while running SMM code

out of DRAM.

3.8.5

SMM Space Decode and Transaction Handling

Only the processor is allowed to access SMM space. PCI Express and DMI Interface

originated transactions are not allowed to SMM space.

3.8.6

Processor WB Transaction to an Enabled SMM Address

Space

Processor Writeback transactions (REQa[1]# = 0) to enabled SMM Address Space

must be written to the associated SMM DRAM even though D_OPEN=0 and the

transaction is not performed in SMM mode. This ensures SMM space cache coherency

when cacheable extended SMM space is used.

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