82G33 datasheet(51/437 Pages) INTEL

51 / 437 page

System Address Map

Datasheet

System Address Map

The (G)MCH supports 64 GB (36 bit) of host address space and 64 KB+3 of

addressable I/O space. There is a programmable memory address space under the

1 MB region that is divided into regions which can be individually controlled with

programmable attributes such as Disable, Read/Write, Write Only, or Read Only.

Attribute programming is described in the Register Description section. This section

focuses on how the memory space is partitioned and what the separate memory

regions are used for. I/O address space has a simpler mapping and is explained in

Section 3.10.

Note: Address mapping information for the Integrated Graphics Device applies to the 82Q35,

82Q33, and 82G33 GMCH only. The 82P35 MCH does not have an IGD.

The (G)MCH supports PEG port upper pre-fetchable base/limit registers. This allows

the PEG unit to claim IO accesses above 36 bit, complying with the PCI Express

Specification. Addressing of greater than 8 GB is allowed on either the DMI Interface

or PCI Express interface. The (G)MCH supports a maximum of 8 GB of DRAM. No

DRAM memory will be accessible above 8 GB.

When running in internal graphics mode (82Q35/82Q33/82G33 GMCH only), writes to

GMADR range linear range are supported. Write accesses to linear regions are

supported from DMI only. Write accesses to tileX and tileY regions are not supported

from DMI or the PEG port. GMADR read accesses are not supported from either DMI or

PEG.

In the following sections, it is assumed that all of the compatibility memory ranges

reside on the DMI Interface. The exception to this rule is VGA ranges, which may be

mapped to PCI-Express, DMI, or to the internal graphics device (IGD). In the absence

of more specific references, cycle descriptions referencing PCI should be interpreted as

the DMI Interface/PCI, while cycle descriptions referencing PCI Express or IGD are

related to the PCI Express bus or the internal graphics device respectively. The

(G)MCH does not remap APIC or any other memory spaces above TOLUD (Top of Low

Usable DRAM). The TOLUD register is set to the appropriate value by BIOS. The

reclaim base/reclaim limit registers remap logical accesses bound for addresses above

4 GB onto physical addresses that fall within DRAM.

82G33 Datasheet(PDF) 51 Page - Intel Corporation