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DRAM Controller Registers (D0:F0)

Datasheet

DRAM Controller Registers

(D0:F0)

5.1

DRAM Controller (D0:F0)

The DRAM Controller registers are in Device 0 (D0), Function 0 (F0).

Warning: Address locations that are not listed are considered Intel Reserved registers locations.

Reads to Reserved registers may return non-zero values. Writes to reserved locations

may cause system failures.

All registers that are defined in the PCI 2.3 specification, but are not necessary or

implemented in this component are simply not included in this document. The

reserved/unimplemented space in the PCI configuration header space is not

documented as such in this summary.

Table 5-1. DRAM Controller Register Address Map (D0:F0)

Address

Offset

Symbol

Default

Value

Access

00–01h

VID

Vendor Identification

8086h

02–03h

DID

Device Identification

29C0h

04–05h

PCICMD

PCI Command

0006h

RO, RW

06–07h

PCISTS

PCI Status

0090h

RWC, RO

08h

RID

Revision Identification

00h

09–0Bh

Class Code

060000h

0Dh

MLT

Master Latency Timer

00h

0Eh

HDR

Header Type

00h

2C–2Dh

SVID

Subsystem Vendor Identification

0000h

RWO

2E–2Fh

SID

Subsystem Identification

0000h

RWO

34h

CAPPTR

Capabilities Pointer

E0h

40–47h

PXPEPBAR

PCI Express Port Base Address

0000000000

000000h

RW/L, RO

48–4Fh

MCHBAR

(G)MCH Memory Mapped Register

Range Base

0000000000

000000h

RW/L, RO

52–53h

GGC

GMCH Graphics Control Register

0030h

RO, RW/L

54–57h

DEVEN

Device Enable

000003DBh

RO, RW/L

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