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82G33 Datasheet(PDF) 27 Page - Intel Corporation |
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82G33 Datasheet(HTML) 27 Page - Intel Corporation |
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27 / 437 page ![]() Introduction Datasheet 27 1.3 (G)MCH Overview The (G)MCH designed for use with the Intel® Core™2 Duo desktop processors and Intel® Core™2 Quad desktop processors in desktop platforms. The role of a (G)MCH in a system is to manage the flow of information between its four interfaces: the processor interface, the System Memory interface, the External Graphics interface, and the I/O Controller through DMI interface. This includes arbitrating between the four interfaces when each initiates transactions. The 82G33 and 82P35 (G)MCHs support one or two channels of DDR2 or DDR3 SDRAM. The 82Q35 and 82Q33 GMCHs support one or two channels of DDR2 SDRAM. The (G)MCH also supports the PCI Express based external graphics attach. The Q35/Q33/G33/P35 Express chipset platforms support the ninth generation I/O Controller Hub (Intel® ICH9) to provide a multitude of I/O related features. 1.3.1 Host Interface The (G)MCH can use a single LGA775 socket processor. The (G)MCH supports FSB frequencies of 200/266/333 MHz. Host-initiated I/O cycles are decoded to PCI Express, DMI, or the (G)MCH configuration space. Host-initiated memory cycles are decoded to PCI Express, DMI, or system memory. PCI Express device accesses to non- cacheable system memory are not snooped on the host bus. Memory accesses initiated from PCI Express using PCI semantics and from DMI to system SDRAM will be snooped on the host bus. Capabilities of the Host Interface include: • Supports Intel® CoreTM2 Duo processors and Intel® CoreTM2 Quad processors • Supports Front Side Bus (FSB) at 800/1066/1333 MT/s (200/266/333 MHz) • Supports FSB Dynamic Bus Inversion (DBI) • Supports 36-bit host bus addressing, allowing the processor to access the entire 64 GB of the host address space • Has a 12-deep In-Order Queue to support up to twelve outstanding pipelined address requests on the host bus • Has a 1-deep Defer Queue • Uses GTL+ bus driver with integrated GTL termination resistors • Supports a Cache Line Size of 64 bytes |
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