82G33 datasheet(80/437 Pages) INTEL

80 / 437 page

(G)MCH Register Description

Datasheet

4.4.1

Internal Device Configuration Accesses

The (G)MCH decodes the Bus Number (bits 23:16) and the Device Number fields of

the CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the

configuration cycle is targeting a PCI Bus #0 device.

If the targeted PCI Bus #0 device exists in the (G)MCH and is not disabled, the

configuration cycle is claimed by the appropriate device.

4.4.2

Bridge Related Configuration Accesses

Configuration accesses on PCI Express or DMI are PCI Express Configuration TLPs.

• Bus Number [7:0] is Header Byte 8 [7:0]

• Device Number [4:0] is Header Byte 9 [7:3]

• Function Number [2:0] is Header Byte 9 [2:0]

And special fields for this type of TLP:

• Extended Register Number [3:0] is Header Byte 10 [3:0]

• Register Number [5:0] is Header Byte 11 [7:2]

See the PCI Express specification for more information on both the PCI 2.3 compatible

and PCI Express Enhanced Configuration Mechanism and transaction rules.

4.4.2.1

PCI Express* Configuration Accesses

When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express

Enhanced Configuration access matches the Device #1 Secondary Bus Number a PCI

Express Type 0 Configuration TLP is generated on the PCI Express link targeting the

device directly on the opposite side of the link. This should be Device #0 on the bus

number assigned to the PCI Express link (likely Bus #1).

The device on other side of link must be Device #0. The (G)MCH will Master Abort any

Type 0 Configuration access to a non-zero Device number. If there is to be more than

one device on that side of the link there must be a bridge implemented in the

downstream device.

When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express

Enhanced Configuration access is within the claimed range (between the upper bound

of the bridge device’s Subordinate Bus Number register and the lower bound of the

bridge device’s Secondary Bus Number register) but doesn't match the Device #1

Secondary Bus Number, a PCI Express Type 1 Configuration TLP is generated on the

secondary side of the PCI Express link.

PCI Express Configuration Writes:

• Internally the host interface unit will translate writes to PCI Express extended

configuration space to configuration writes on the backbone.

• Writes to extended space are posted on the FSB, but non-posted on the PCI

Express or DMI (i.e., translated to configuration writes)

82G33 Datasheet(PDF) 80 Page - Intel Corporation

82G33 Datasheet(HTML) 80 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL