82G33 datasheet(4/437 Pages) INTEL

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Datasheet

3.3

PCI Memory Address Range (TOLUD – 4GB) .............................................61

3.3.1

APIC Configuration Space (FEC0_0000h–FECF_FFFFh) ..................63

3.3.2

HSEG (FEDA_0000h–FEDB_FFFFh).............................................63

3.3.3

FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) .................63

3.3.4

High BIOS Area.......................................................................63

3.4

Main Memory Address Space (4 GB to TOUUD) .........................................64

3.4.1

Memory Re-claim Background ...................................................65

3.4.2

Memory Reclaiming .................................................................65

3.5

PCI Express* Configuration Address Space...............................................65

3.6

PCI Express* Graphics Attach (PEG)........................................................66

3.7

Graphics Memory Address Ranges (Intel® 82Q35, 82Q33, and 82G33

(G)MCH Only) ......................................................................................67

3.8

System Management Mode (SMM) ..........................................................67

3.8.1

SMM Space Definition ..............................................................68

3.8.2

SMM Space Restrictions............................................................68

3.8.3

SMM Space Combinations .........................................................69

3.8.4

SMM Control Combinations .......................................................69

3.8.5

SMM Space Decode and Transaction Handling..............................69

3.8.6

Processor WB Transaction to an Enabled SMM Address Space ........69

3.8.7

SMM Access through GTT TLB (Intel® 82Q35, 82Q33, 82G33

GMCH Only) ...........................................................................70

3.9

Memory Shadowing ..............................................................................70

3.10

I/O Address Space................................................................................70

3.10.1

PCI Express* I/O Address Mapping ............................................71

3.11

(G)MCH Decode Rules and Cross-Bridge Address Mapping ..........................72

3.11.1

Legacy VGA and I/O Range Decode Rules ...................................72

(G)MCH Register Description ............................................................................73

4.1

4.2

Configuration Process and Registers........................................................76

4.2.1

Platform Configuration Structure ...............................................76

4.3

Configuration Mechanisms .....................................................................77

4.3.1

Standard PCI Configuration Mechanism ......................................77

4.3.2

PCI Express* Enhanced Configuration Mechanism ........................77

4.4

Routing Configuration Accesses ..............................................................79

4.4.1

Internal Device Configuration Accesses.......................................80

4.4.2

Bridge Related Configuration Accesses........................................80

4.4.2.1

PCI Express* Configuration Accesses ...........................80

4.4.2.2

DMI Configuration Accesses .......................................81

4.5

I/O Mapped Registers ...........................................................................81

4.5.1

CONFIG_ADDRESS—Configuration Address Register.....................81

4.5.2

CONFIG_DATA—Configuration Data Register ...............................83

DRAM Controller Registers (D0:F0)....................................................................85

5.1

DRAM Controller (D0:F0).......................................................................85

5.1.1

VID—Vendor Identification........................................................87

5.1.2

DID—Device Identification ........................................................87

5.1.3

PCICMD—PCI Command...........................................................88

5.1.4

PCISTS—PCI Status .................................................................89

5.1.5

RID—Revision Identification......................................................90

5.1.6

CC—Class Code.......................................................................91

5.1.7

MLT—Master Latency Timer ......................................................91

5.1.8

HDR—Header Type ..................................................................92

82G33 Datasheet(PDF) 4 Page - Intel Corporation

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