82G33 datasheet(71/437 Pages) INTEL

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System Address Map

Datasheet

The processor allows 64 K+3 bytes to be addressed within the I/O space. The (G)MCH

propagates the processor I/O address without any translation on to the destination

bus and therefore provides addressability for 64K+3 byte locations. Note that the

upper 3 locations can be accessed only during I/O address wrap-around when

processor bus HAB_16 address signal is asserted. HAB_16 is asserted on the

processor bus whenever an I/O access is made to 4 bytes from address 0FFFDh,

0FFFEh, or 0FFFFh. HAB_16 is also asserted when an I/O access is made to 2 bytes

from address 0FFFFh.

A set of I/O accesses (other than ones used for configuration space access) are

consumed by the internal graphics device if it is enabled. The mechanisms for internal

graphics I/O decode and the associated control is explained later.

The I/O accesses (other than ones used for configuration space access) are forwarded

normally to the DMI Interface bus unless they fall within the PCI Express I/O address

range as defined by the mechanisms explained below. I/O writes are NOT posted.

Memory writes to ICH9 or PCI Express are posted. The PCICMD1 register can disable

the routing of I/O cycles to the PCI Express.

The (G)MCH responds to I/O cycles initiated on PCI Express or DMI with an UR status.

Upstream I/O cycles and configuration cycles should never occur. If one does occur,

the request will route as a read to memory address 000C_0000h so a completion is

naturally generated (whether the original request was a read or write). The

transaction will complete with an UR completion status.

For Pentium® 4 processors, I/O reads that lie within 8-byte boundaries but cross 4-

byte boundaries are issued from the processor as 1 transaction. The (G)MCH breaks

this into 2 separate transactions. I/O writes that lie within 8-byte boundaries but cross

4-byte boundaries are assumed to be split into 2 transactions by the processor.

3.10.1

PCI Express* I/O Address Mapping

The (G)MCH can be programmed to direct non-memory (I/O) accesses to the PCI

Express bus interface when processor initiated I/O cycle addresses are within the PCI

Express I/O address range. This range is controlled via the I/O Base Address

(IOBASE) and I/O Limit Address (IOLIMIT) registers in (G)MCH Device 1 configuration

space.

Address decoding for this range is based on the following concept. The top 4 bits of

the respective I/O Base and I/O Limit registers correspond to address bits A[15:12] of

an I/O address. For the purpose of address decoding, the (G)MCH assumes that lower

12 address bits A[11:0] of the I/O base are zero and that address bits A[11:0] of the

I/O limit address are FFFh. This forces the I/O address range alignment to 4 KB

boundary and produces a size granularity of 4 KB.

The (G)MCH positively decodes I/O accesses to PCI Express I/O address space as

defined by the following equation:

I/O_Base_Address ≤ Processor I/O Cycle Address ≤ I/O_Limit_Address

The effective size of the range is programmed by the plug-and-play configuration

software and it depends on the size of I/O space claimed by the PCI Express device.

The (G)MCH also forwards accesses to the Legacy VGA I/O ranges according to the

settings in the Device 1 configuration registers BCTRL (VGA Enable) and PCICMD1

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