82G33 datasheet(88/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

5.1.3

PCICMD—PCI Command

B/D/F/Type:

0/0/0/PCI

Address Offset:

4–5h

Default Value:

0006h

Access:

RO, RW

Size:

16 bits

Since (G)MCH Device 0 does not physically reside on PCI_A many of the bits are not

implemented.

Bit

Access &

Default

Description

15:10

00h

Reserved

Fast Back-to-Back Enable (FB2B): This bit controls whether or not

the master can do fast back-to-back write. Since device 0 is strictly a

target, this bit is not implemented and is hardwired to 0.

SERR Enable (SERRE): This bit is a global enable bit for Device 0

SERR messaging. The (G)MCH does not have an SERR signal. The

(G)MCH communicates the SERR condition by sending an SERR

message over DMI to the ICH.

1= The (G)MCH is enabled to generate SERR messages over DMI for

specific Device 0 error conditions that are individually enabled in

the ERRCMD and DMIUEMSK registers. The error status is reported

in the ERRSTS, PCISTS, and DMIUEST registers.

0 =The SERR message is not generated by the (G)MCH for Device 0.

Note that this bit only controls SERR messaging for the Device 0.

Device 1 has its own SERRE bits to control error reporting for error

conditions occurring in that device. The control bits are used in a

logical OR manner to enable the SERR DMI message mechanism.

Address/Data Stepping Enable (ADSTEP): Address/data stepping

is not implemented in the (G)MCH, and this bit is hardwired to 0.

Parity Error Enable (PERRE): This bit controls whether or not the

Master Data Parity Error bit in the PCI Status register can bet set.

0= Master Data Parity Error bit in PCI Status register can NOT be set.

1 = Master Data Parity Error bit in PCI Status register CAN be set.

VGA Palette Snoop Enable (VGASNOOP): The (G)MCH does not

implement this bit and it is hardwired to a 0.

Memory Write and Invalidate Enable (MWIE): The (G)MCH will

never issue memory write and invalidate commands. This bit is

therefore hardwired to 0.

Special Cycle Enable (SCE): The (G)MCH does not implement this bit

and it is hardwired to a 0. Writes to this bit position have no effect.

Bus Master Enable (BME): The (G)MCH is always enabled as a

master on the backbone. This bit is hardwired to a 1.

Memory Access Enable (MAE): The (G)MCH always allows access to

main memory. This bit is not implemented and is hardwired to 1.

I/O Access Enable (IOAE): This bit is not implemented in the

(G)MCH and is hardwired to a 0.

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