82G33 datasheet(28/437 Pages) INTEL

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Introduction

Datasheet

1.3.2

System Memory Interface

The (G)MCH integrates a system memory DDR2 and DDR3 (82G33 GMCH and 82P35

MCH only) controller with two, 64-bit wide interfaces. The buffers support both

SSTL_1.8 (Stub Series Terminated Logic for 1.8 V) and SSTL_1.5 (Stub Series

Terminated Logic for 1.5 V) signal interfaces. The memory controller interface is fully

configurable through a set of control registers.

Capabilities of the system memory interface include:

• Directly supports one or two channels of DDR2 or DDR3 (82G33 GMCH and 82P35

MCH only) memory with a maximum of two DIMMs per channel.

• Supports single and dual channel memory organization modes.

• Supports a data burst length of eight for all memory organization modes.

• Supports memory data transfer rates of 667 MHz and 800 MHz for DDR2, and

800 MHz and 1066 MHz for DDR3.

• I/O Voltage of 1.8 V for DDR2 and 1.5 V for DDR3.

• Supports only un-buffered non-ECC DDR2 or DDR3 DIMMs

• Supports maximum memory bandwidth of 6.4 GB/s in single-channel or dual-

channel asymmetric mode, or 12.8 GB/s in dual-channel symmetric mode

assuming DDR2 800 MHz.

• Supports maximum memory bandwidth of 8.5 GB/s in single-channel or dual-

channel asymmetric mode, or 17 GB/s in dual-channel interleaved mode assuming

DDR3 1066 MHz.

• Supports 512 Mb and 1 Gb DDR2 or DDR3 (82G33 GMCH and 82P35 MCH only)

DRAM technologies for x8 and x16 devices.

• Using 512 Mb device technologies, the smallest memory capacity possible is

256 MB, assuming Single Channel Mode with a single x16 single sided un-buffered

non-ECC DIMM memory configuration.

• Using 1 Gb device technologies, the largest memory capacity possible is 8 GB,

assuming Dual Channel Mode with four x8 double sided un-buffered non-ECC

DIMM memory configuration.

• Supports up to 32 simultaneous open pages per channel (assuming 4 ranks of

8 bank devices).

• Supports opportunistic refresh scheme. The (G)MCH has an arbitration scheme to

refresh memory when the DRAM is idle.

• Supports Partial Writes to memory using Data Mask (DM) signals.

• Supports a memory thermal management scheme to selectively manage reads

and/or writes. Memory thermal management can be triggered either by on-die

thermal sensor, or by preset limits. Management limits are determined by

weighted sum of various commands that are scheduled on the memory interface.

82G33 Datasheet(PDF) 28 Page - Intel Corporation