82G33 datasheet(40/437 Pages) INTEL

40 / 437 page

Signal Description

Datasheet

2.2

System Memory (DDR2/DDR3) Channel A

Interface Signals

Note: DDR3 is only supported on the 82G33 GMCH and 82P35 MCH components.

Signal Name

Type

Description

DDR_A_CK_5:0

SSTL-1.8/1.5

SDRAM Differential Clocks

• DDR2: Three per DIMM (5:0)

• DDR3: Two per DIMM (3:0)

DDR_A_CKB_5:0

SSTL-1.8/1.5

SDRAM Inverted Differential Clocks

• DDR2: Three per DIMM (5:0)

• DDR3: Two per DIMM (3:0)

DDR_A_CSB_3:0

SSTL-1.8/1.5

DDR2/DDR3 Device Rank 3, 2, and 0 chip

selects

DDR2 Device Rank 1 chip select

DDR3_A_CSB_1

SSTL-1.5

DDR3 Device Rank 1 Chip Select

DDR_A_CKE_3:0

SSTL-1.8/1.5

DDR2/DDR3 Clock Enable

(1 per Device Rank)

DDR_A_ODT_3:0

SSTL-1.8/1.5

DDR2/DDR3 On Die Termination

(1 per Device Rank)

DDR_A_MA_14:1

SSTL-1.8/1.5

DDR2/DDR3 Address Signals 14:1

DDR_A_MA_0

SSTL-1.8

DDR2 Address Signals 0

DDR3_A_MA_0

SSTL-1.5

DDR3 Address Signal 0

DDR_A_BS_2:0

SSTL-1.8/1.5

DDR2/DDR3 Bank Select

DDR_A_RASB

SSTL-1.8/1.5

DDR2/DDR3 RAS signal

DDR_A_CASB

SSTL-1.8/1.5

DDR2/DDR3 CAS signal

DDR_A_WEB

SSTL-1.8

DDR2 Write Enable signal

DDR3_A_WEB

SSTL-1.5

DDR3 Write Enable signal

DDR_A_DQ_63:0

I/O

SSTL-1.8/1.5

DDR2/DDR3 Data Lines

DDR_A_DM_7:0

SSTL-1.8/1.5

DDR2/DDR3 Data Mask

DDR_A_DQS_7:0

I/O

SSTL-1.8/1.5

DDR2/DDR3 Data Strobes

DDR_A_DQSB_7:0

I/O

SSTL-1.8/1.5

DDR2/DDR3 Data Strobe Complements

82G33 Datasheet(PDF) 40 Page - Intel Corporation

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