82G33 datasheet(77/437 Pages) INTEL

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(G)MCH Register Description

Datasheet

4.3

Configuration Mechanisms

The processor is the originator of configuration cycles so the FSB is the only interface

in the platform where these mechanisms are used. Internal to the (G)MCH

transactions received through both configuration mechanisms are translated to the

same format.

4.3.1

Standard PCI Configuration Mechanism

The following is the mechanism for translating processor I/O bus cycles to

configuration cycles.

The PCI specification defines a slot based "configuration space" that allows each

device to contain up to 8 functions with each function containing up to 256 8-bit

configuration registers. The PCI specification defines two bus cycles to access the PCI

configuration space: Configuration Read and Configuration Write. Memory and I/O

spaces are supported directly by the processor. Configuration space is supported by a

mapping mechanism implemented within the (G)MCH.

The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at

I/O address 0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh

though 0CFFh). To reference a configuration register a DWord I/O write cycle is used

to place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that

bus, the function within the device and a specific configuration register of the device

function being accessed. CONFIG_ADDRESS[31] must be 1 to enable a configuration

cycle. CONFIG_DATA then becomes a window into the four bytes of configuration

space specified by the contents of CONFIG_ADDRESS. Any read or write to

CONFIG_DATA will result in the (G)MCH translating the CONFIG_ADDRESS into the

appropriate configuration cycle.

The (G)MCH is responsible for translating and routing the processor’s I/O accesses to

the CONFIG_ADDRESS and CONFIG_DATA registers to internal (G)MCH configuration

registers, DMI or PCI Express.

4.3.2

PCI Express* Enhanced Configuration Mechanism

PCI Express extends the configuration space to 4096 bytes per device/function as

compared to 256 bytes allowed by PCI Specification Revision 2.3. PCI Express

configuration space is divided into a PCI 2.3 compatible region, which consists of the

first 256B of a logical device’s configuration space and a PCI Express extended region

which consists of the remaining configuration space.

The PCI compatible region can be accessed using either the Standard PCI

Configuration Mechanism or using the PCI Express Enhanced Configuration Mechanism

described in this section. The extended configuration registers may only be accessed

using the PCI Express Enhanced Configuration Mechanism. To maintain compatibility

with PCI configuration addressing mechanisms, system software must access the

extended configuration space using 32-bit operations (32-bit aligned) only. These 32-

bit operations include byte enables allowing only appropriate bytes within the DWord

to be accessed. Locked transactions to the PCI Express memory mapped configuration

address space are not supported. All changes made using either access mechanism

are equivalent.

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