82G33 datasheet(72/437 Pages) INTEL

72 / 437 page

System Address Map

Datasheet

(IOAE1), unless a second adapter (monochrome) is present on the DMI Interface/PCI

(or ISA). The presence of a second graphics adapter is determined by the MDAP

configuration bit. When MDAP is set, the (G)MCH will decode legacy monochrome I/O

ranges and forward them to the DMI Interface. The IO ranges decoded for the

monochrome adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3Bah and 3BFh.

Note that the (G)MCH Device 1 I/O address range registers defined above are used for

all I/O space allocation for any devices requiring such a window on PCI Express.

The PCICMD1 register can disable the routing of I/O cycles to PCI Express.

3.11

(G)MCH Decode Rules and Cross-Bridge Address

Mapping

VGAA = 000A_0000 – 000A_FFFF

MDA = 000B_0000 – 000B_7FFF

VGAB = 000B_8000 – 000B_FFFF

MAINMEM = 0100_0000 to TOLUD

HIGHMEM = 4 GB to TOM

RECLAIMMEM = RECLAIMBASE to RECLAIMLIMIT

3.11.1

Legacy VGA and I/O Range Decode Rules

The legacy 128 KB VGA memory range 000A_0000h-000B_FFFFh can be mapped to

IGD (Device 2), to PCI Express (Device 1), and/or to the DMI Interface depending on

the programming of the VGA steering bits. Priority for VGA mapping is constant in that

the (G)MCH always decodes internally mapped devices first. Internal to the GMCH,

decode precedence is always given to IGD. The GMCH always positively decodes

internally mapped devices, namely the IGD and PCI-Express. Subsequent decoding of

regions mapped to PCI Express or the DMI Interface depends on the Legacy VGA

configurations bits (VGA Enable and MDAP).

82G33 Datasheet(PDF) 72 Page - Intel Corporation