82G33 datasheet(46/437 Pages) INTEL

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Signal Description

Datasheet

Signal Name

Type

Description

EXP_EN

CMOS

Concurrent PCI Express Port Enable: This signal selects

Concurrent SDVO and PCI Express

0 = Only SDVO or PCI Express is operational.

1 = Both SDVO and PCI Express are operating

simultaneously via the PCI Express port.

NOTES: For the 82P35 MCH, this signal should be pulled low.

PWROK

I/O

HVIN

Power OK: When asserted, PWROK is an indication to the

(G)MCH that core power has been stable for at least 10 us.

ICH_SYNCB

HVCMOS

ICH Sync: Maintains synchronization between (G)MCH and

ICH9. This signal is connected to the MCH_SYNC# signal on

the ICH.

ALLZTEST/

XORTEST

I/O

CMOS

All Z Test: ALLZTEST is used for chipset Bed of Nails testing

to execute All Z Test.

XOR Chain Test: XORTEST is used for Chipset Bed of Nails

testing to execute XOR Chain Test.

XORTEST

ALLZTEST

Description

(Ball F20)

(Ball K20)

Reserved

XORTEST. Used for chipset Bed

of Nails Testing to execute XOR

Chain Test.

All pins tri-stated. Used for

chipset testing.

Normal

TEST[2:0]

I/O

In Circuit Test: These pins should be connected to test

points on the motherboard. They are internally shorted to the

package ground and can be used to determine if the corner

balls on the (G)MCH are correctly soldered down to the

motherboard.

These pins should NOT connect to ground on the

motherboard.

If TEST[2:0] are not going to be used, they should be left as

no connects.

2.9

Direct Media Interface

Signal Name

Type

Description

DMI_RXP_3:0

DMI_RXN_3:0

DMI

Direct Media Interface: Receive differential pair (RX). These

signals are the (G)MCH-ICH9 serial interface input.

DMI_TXP_3:0

DMI_TXN_3:0

DMI

Direct Media Interface: Transmit differential pair (TX). These

signals are the (G)MCH-ICH9 serial interface output.

82G33 Datasheet(PDF) 46 Page - Intel Corporation

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