82G33 datasheet(98/437 Pages) INTEL

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DRAM Controller Registers (D0:F0)

Datasheet

Bit

Access &

Default

Description

Reserved

RW/L

82Q35, 82Q33, 82G33 GMCH

Internal Graphics Engine Function 1 (D2F1EN):

0 = Bus 0, Device 2, Function 1 is disabled and hidden

1 = Bus 0, Device 2, Function 1 is enabled and visible

If Device 2, Function 0 is disabled and hidden, then Device 2, Function

1 is also disabled and hidden independent of the state of this bit.

If this component is not capable of Dual Independent Display

(CAPID0[78] = 1), then this bit is hardwired to 0b to hide Device 2,

Function 1.

82P35 MCH

Reserved

RW/L

82Q35, 82Q33, 82G33 GMCH

Internal Graphics Engine Function 0 (D2F0EN):

0 = Bus 0, Device 2, Function 0 is disabled and hidden

1 = Bus 0, Device 2, Function 0 is enabled and visible

If this GMCH does not have internal graphics capability (CAPID0[46] =

1), then Device 2, Function 0 is disabled and hidden independent of

the state of this bit.

82P35 MCH

Reserved

RW/L

PCI Express Port (D1EN):

0 = Bus 0, Device 1, Function 0 is disabled and hidden.

1 = Bus 0, Device 1, Function 0 is enabled and visible.

Default value is determined by the device capabilities (see CAPID0

[44]), SDVO Presence hardware strap and the SDVO/PCI Express

Concurrent hardware strap. Device 1 is Disabled on Reset if the SDVO

Presence strap was sampled high, and the SDVO/PCI Express

Concurrent strap was sampled low at the last assertion of PWROK, and

is enabled by default otherwise.

Host Bridge (D0EN): Bus 0, Device 0, Function 0 may not be

disabled and is therefore hardwired to 1.

82G33 Datasheet(PDF) 98 Page - Intel Corporation