82G33 datasheet(58/437 Pages) INTEL

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System Address Map

Datasheet

3.1.5

System BIOS Area (F_0000h-F_FFFFh)

This area is a single 64 KB segment (000F_0000h – 000F_FFFFh). This segment can

be assigned read and write attributes. It is by default (after reset) read/write disabled

and cycles are forwarded to DMI Interface. By manipulating the read/write attributes,

the (G)MCH can “shadow” BIOS into the main DRAM. When disabled, this segment is

not remapped.

Non-snooped accesses from PCI Express or DMI to this region are always sent to

DRAM.

Table 3-3. System BIOS Area Memory Segments

Memory Segments

Attributes

Comments

0F0000h – 0FFFFFh

WE RE

BIOS Area

3.1.6

PAM Memory Area Details

The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM

memory area.

The (G)MCH does not handle IWB (Implicit Write-Back) cycles targeting DMI. Since all

memory residing on DMI should be set as non-cacheable, there will normally not be

IWB cycles targeting DMI. However, DMI becomes the default target for processor and

DMI originated accesses to disabled segments of the PAM region. If the MTRRs

covering the PAM regions are set to WB or RD it is possible to get IWB cycles targeting

DMI. This may occur for processor originated cycles and for DMI originated cycles to

disabled PAM regions.

For example, say that a particular PAM region is set for “Read Disabled” and the MTRR

associated with this region is set to WB. A DMI master generates a memory read

targeting the PAM region. A snoop is generated on the FSB and the result is an IWB.

Since the PAM region is “Read Disabled” the default target for the Memory Read

becomes DMI. The IWB associated with this cycle will cause the (G)MCH to hang.

Non-snooped accesses from PCI Express or DMI to this region are always sent to

DRAM.

82G33 Datasheet(PDF) 58 Page - Intel Corporation