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82G33 Datasheet(PDF) 95 Page - Intel Corporation |
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82G33 Datasheet(HTML) 95 Page - Intel Corporation |
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95 / 437 page  DRAM Controller Registers (D0:F0) Datasheet 95 5.1.14 GGC—GMCH Graphics Control Register (Intel® 82Q35, 82Q33, 82G33 GMCH Only) B/D/F/Type: 0/0/0/PCI Address Offset: 52–53h Default Value: 0030h Access: RO, RW/L Size: 16 bits All the bits in this register are Intel® TXT lockable. Bit Access & Default Description 15:10 RO 00h Reserved 9:8 RW/L 0h GTT Graphics Memory Size (GGMS): This field is used to select the amount of main memory that is pre-allocated to support the Internal Graphics Translation Table. The BIOS ensures that memory is pre- allocated only when Internal graphics is enabled. 00 = No memory pre-allocated. GTT cycles (Memory and I/O) are not claimed. 01 = No VT mode, 1 MB of memory pre-allocated for GTT. 10 = VT mode, 2 MB of memory pre-allocated for GTT. 11 = Reserved Note: This register is locked and becomes Read Only when the D_LCK bit in the SMRAM register is set. |
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