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XIO2221 Datasheet(PDF) 23 Page - Texas Instruments |
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XIO2221 Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 196 page  XIO2221 www.ti.com SCPS216A – JULY 2009 – REVISED FEBRAURY 2010 Table 2-4. Ground Terminals I/O SIGNAL BALL NO. DESCRIPTION TYPE VSS A07 A14 GND Digital ground for link VSSA B06 C10 F05 GND Analog ground for link VSSA_PCIE C04 C05 C06 C07 GND Analog ground for PCIe function PLLGND N05 GND PLL circuit ground. This terminal must be tied to the low-impedance circuit-board ground plane. GND E06 E07 F06 F07 F08 F09 GND Ground. These terminals must be tied together to the low-impedance G05 G06 G07 G08 G09 H05 circuit-board ground plane. H06 H07 H08 H09 J05 J06 J07 J08 K05 K06 K07 K08 Table 2-5. PCIe Terminals I/O EXTERNAL SIGNAL BALL NO. DESCRIPTION TYPE PARTS PERST B13 I PCI Express reset. PERST identifies when the system power is stable and generates an internal power-on reset. Note: The PERST input buffer has hysteresis. REF0_PCIE A13 I/O External External reference resistor + and terminals for setting TX driver current. An REF1_PCIE A12 resistor external resistor is connected between terminals REF0_PCIE and REF1_PCIE. RXP A04 DI High-speed receive pair. RXP and RXN comprise the differential receive pair RXN A03 for the single PCIe lane supported. TXP A09 DO Series High-speed transmit pair. TXP and TXN comprise the differential transmit pair TXN A08 capacitors for the single PCIe lane supported. Table 2-6. Clock Terminals I/O EXTERNAL SIGNAL BALL NO. DESCRIPTION TYPE PARTS REFCLK_SEL H13 I Pullup or Reference clock select. This terminal selects the reference clock input. pulldown 0 = 100-MHz differential common reference clock used resistor 1 = 125-MHz single-ended reference clock used REFCLK+ A01 DI Reference clock positive. REFCLK+ and REFCLK– comprise the differential input pair for the 100-MHz system reference clock. For a single-ended, 125-MHz system reference clock, use the REFCLK+ input. REFCLK– B01 DI Capacitor to Reference clock negative. REFCLK+ and REFCLK– comprise the differential VSS for input pair for the 100-MHz system reference clock. For a single-ended, single-ended 125-MHz system reference clock, attach a capacitor from REFCLK– to VSS. mode CLKREQ J12 O Clock request. This terminal is used to support the clock request protocol. XI P04 I Oscillator input. This terminal connects to a 98.304-MHz low-jitter external oscillator. XI is a 1.8-V CMOS input. Oscillator jitter must be 5-ps RMS or better. If only 3.3-V oscillators can be acquired, great care must be taken to not introduce significant jitter by the means used to level shift from 3.3 V to 1.8 V. If a resistor divider is used, a high-current oscillator and low-value resistors must be used to minimize RC time constants. Copyright © 2009–2010, Texas Instruments Incorporated Overview 23 Submit Documentation Feedback Product Folder Link(s): XIO2221 |
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