XIO2221 datasheet(35/196 Pages) TI1

35 / 196 page

SCL

SDA

VDD_33

SCL

SDA

XIO2221

Serial

EEPROM

XIO2221

www.ti.com

SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

3.5

Two-Wire Serial-Bus Interface

The bridge provides a two-wire serial-bus interface to load subsystem identification information and

specific register defaults from an external EEPROM. The serial-bus interface signals are SCL and SDA.

3.5.1

Serial-Bus Interface Implementation

To enable the serial-bus interface, a pullup resistor must be implemented on the SDA signal. At the rising

edge of PERST or GRST, whichever occurs later in time, the SDA terminal is checked for a pullup

resistor. If one is detected, bit 3 (SBDETECT) in the serial-bus control and status register (see

Section 4.59) is set. Software may disable the serial-bus interface at any time by writing a 0b to the

SBDETECT bit. If no external EEPROM is required, the serial-bus interface is permanently disabled by

attaching a pulldown resistor to the SDA signal.

The bridge implements a two-terminal serial interface with one clock signal (SCL) and one data signal

(SDA). The SCL signal is a unidirectional output from the bridge and the SDA signal is bidirectional. Both

are open-drain signals and require pullup resistors. The bridge is a bus master device and drives SCL at

approximately 60 kHz during data transfers and places SCL in a high-impedance state (0 frequency)

during bus idle states. The serial EEPROM is a bus slave device and must acknowledge a slave address

equal to A0h. Figure 3-6 shows an example application implementing the two-wire serial bus.

Figure 3-6. Serial EEPROM Application

Feature/Protocol Descriptions

Submit Documentation Feedback

Product Folder Link(s): XIO2221

XIO2221 Datasheet(PDF) 35 Page - Texas Instruments