XIO2221 datasheet(52/196 Pages) TI1

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XIO2221

SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

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4.14 Subordinate Bus Number Register

This read/write register specifies the bus number of the highest-number PCI bus segment that is

downstream of the bridge. Since the PCI bus is internal and only connects to the 1394a OHCI, this

bridge uses this register to determine how to respond to a type 1 configuration transaction.

PCI register offset:

1Ah

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

4.15 Secondary Latency Timer Register

This read/write register specifies the secondary bus latency timer for the bridge, in units of PCI clock

cycles.

PCI register offset:

1Bh

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

4.16 I/O Base Register

This read/write register specifies the lower limit of the I/O addresses that the bridge forwards downstream.

See Table 4-7 for a complete description of the register contents.

PCI register offset:

1Ch

Read only, Read/Write

Default value:

01h

BIT NUMBER

RESET STATE

Table 4-7. I/O Base Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:4

IOBASE

3:0

IOTYPE

I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.

Classic PCI Configuration Space

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