XIO2221 datasheet(87/196 Pages) TI1

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XIO2221

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SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

Table 4-40. General Control Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

19(1)

READ_

Read prefetch disable. This bit controls the prefetch functionality on PCI memory read

PREFETCH_ DIS

transactions.

0 = Prefetch to the next cache line boundary on a burst read (default)

1 = Fetch only a single DWORD on a burst read

Note: When this bit is set, the PREFETCH_4X bit in the TL control and diagnostic register shall

have no effect on the design. This bit shall only affect the XIO2221 when the

EN_CACHE_LINE_CHECK bit in the TL control and diagnostic register is set.

18:16(1)

L0s_LATENCY

L0s maximum exit latency. This field programs the maximum acceptable latency when exiting the

L0s state. This sets bits 8:6 (EP_L0S_LAT) in the device capabilities register (offset 94h, see

Section 4.50).

000 = Less than 64 ns (default)

001 = 64 ns up to less than 128 ns

010 = 128 ns up to less than 256 ns

011 = 256 ns up to less than 512 ns

100 = 512 ns up to less than 1 s

101 = 1 s up to less than 2 s

110 = 2 s to 4 s

111 = More than 4 s

15:13(3)

L1_LATENCY

L1 maximum exit latency. This field programs the maximum acceptable latency when exiting the

L1 state. This sets bits 11:9 (EP_L1_LAT) in the device capabilities register (offset 94h, see

Section 4.50).

000 = Less than 1 s (default)

001 = 1 s up to less than 2 s

010 = 2 s up to less than 4 s

011 = 4 s up to less than 8 s

100 = 8 s up to less than 16 s

101 = 6 s up to less than 32 s

110 = 32 s to 64 s

111 = More than 64 s

12(3)

VC_CAP_EN

VC capability structure enable. This bit enables the VC capability structure by changing the next

offset field of the advanced error reporting capability register at offset 102h. This bit is a read only

0b indicating that the VC capability structure is permanently disabled.

0 = VC capability structure disabled (offset field = 000h)

1 = VC capability structure enabled (offset field = 150h)

11(3)

BPCC_E

Bus power clock control enable. This bit controls whether the secondary bus PCI clocks are

stopped when the XIO2221 is placed in the D3 state. It is assumed that if the secondary bus

clocks are required to be active that a reference clock continues to be provided on the PCIe

interface.

0 = Secondary bus clocks are not stopped in D3 (default).

1 = Secondary bus clocks are stopped on D3.

10(4)

BEACON_

Beacon enable. This bit controls the mechanism for waking up the physical PCIe link when in L2.

ENABLE

0 = WAKE mechanism is used exclusively. Beacon is not used (default).

1 = Beacon and WAKE mechanisms are used.

9:8(3)

MIN_POWER_

Minimum power scale. This value is programmed to indicate the scale of bits 7:0

SCALE

(MIN_POWER_VALUE).

00 = 1.0x

01 = 0.1x

10 = 0.01x (default)

11 = 0.001x

7:0(3)

MIN_POWER_

Minimum power value. This value is programmed to indicate the minimum power requirements.

VALUE

This value is multiplied by the minimum power scale field (bits 9:8) to determine the minimum

power requirements for the bridge. The default is 5Fh, indicating that XIO2221 requires 0.95 W of

power. This field can be reprogrammed through an EEPROM or the system BIOS.

(3)

These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

(4)

These bits are reset only by a global reset (GRST) or the internally generated power-on reset.

Classic PCI Configuration Space

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