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XIO2221 Datasheet(PDF) 55 Page - Texas Instruments |
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XIO2221 Datasheet(HTML) 55 Page - Texas Instruments |
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55 / 196 page  XIO2221 www.ti.com SCPS216A – JULY 2009 – REVISED FEBRAURY 2010 4.19 Memory Base Register This read/write register specifies the lower limit of the memory addresses that the bridge forwards downstream. See Table 4-10 for a complete description of the register contents. PCI register offset: 20h Register type: Read only, Read/Write Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-10. Memory Base Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:4 MEMBASE RW Memory base. Defines the lowest address of the memory address range that determines when to forward memory transactions from one interface to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be 00000h. 3:0 RSVD R Reserved. Returns 0h when read. 4.20 Memory Limit Register This read/write register specifies the upper limit of the memory addresses that the bridge forwards downstream. See Table 4-11 for a complete description of the register contents. PCI register offset: 22h Register type: Read only, Read/Write Default value: 0000h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4-11. Memory Limit Register Description BIT FIELD NAME ACCESS DESCRIPTION 15:4 MEMLIMIT RW Memory limit. Defines the highest address of the memory address range that determines when to forward memory transactions from one interface to the other. These bits correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be FFFFFh. 3:0 RSVD R Reserved. Returns 0h when read. Copyright © 2009–2010, Texas Instruments Incorporated Classic PCI Configuration Space 55 Submit Documentation Feedback Product Folder Link(s): XIO2221 |
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