XIO2221 datasheet(15/196 Pages) TI1

15 / 196 page

XIO2221

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SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

The XIO2221 requires an external 98.304-MHz crystal oscillator to generate a reference clock. The

external clock drives an internal phase-locked loop (PLL), which generates the required reference signal.

This reference signal provides the clock signals that control transmission of the outbound encoded

information. The power-down (PD) function, when enabled by asserting the PD terminal high, stops

operation of the PLL. Data bits to be transmitted through the cable ports are latched internally, combined

serially, encoded, and transmitted at 98.304, 196.608, 393.216, 491.52, or 983.04 Mbit/s (referred to as

S100, S200, S400, S400B, or S800 speed, respectively) as the outbound information stream.

To ensure that the XIO2221 conforms to IEEE Std 1394b-2002, the BMODE terminal must be asserted.

The BMODE terminal does not select the cable-interface mode of operation. BMODE selects the internal

PHY-section/LLC-section interface mode of operation and affects the arbitration modes on the cable.

BMODE must be pulled high during normal operation.

Three package terminals are used as inputs to set the default value for three configuration status bits in

the self-ID packet. They can be pulled high through a 1-k

Ω resistor or hardwired low as a function of the

equipment design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node

(the need for power from the cable or the ability to supply power to the cable). The contender bit in the

PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM)

or for the bus manager (BM). On the XIO2221, this bit can only be set by a write to the PHY register set. If

a node is to be a contender for IRM or BM, the node software must set this bit in the PHY register set.

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XIO2221 Datasheet(PDF) 15 Page - Texas Instruments