XIO2221 datasheet(94/196 Pages) TI1

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XIO2221

SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

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5.2

Next Capability Offset/Capability Version Register

This read-only register identifies the next location in the PCIe extended capabilities link list. The upper 12

bits in this register shall be 000h, indicating that the advanced error reporting capability is the last

capability in the linked list. The least significant four bits identify the revision of the current capability block

as 1h.

PCIe extended register

102h

offset:

Read only

Default value:

0001h

BIT NUMBER

RESET STATE

5.3

Uncorrectable Error Status Register

The uncorrectable error status register reports the status of individual errors as they occur on the primary

PCIe interface. Software may only clear these bits by writing a 1b to the desired location. See Table 5-2

for a complete description of the register contents.

PCIe extended register

104h

offset:

Read only, Read/Clear

Default value:

0000h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 5-2. Uncorrectable Error Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:21

RSVD

Reserved. Returns 000 0000 0000b when read.

20(1)

UR_ERROR

RCU

Unsupported request error. This bit is asserted when an unsupported request is received.

19(1)

ECRC_ERROR

RCU

Extended CRC error. This bit is asserted when an extended CRC error is detected.

18(1)

MAL_TLP

RCU

Malformed TLP. This bit is asserted when a malformed TLP is detected.

17(1)

RX_OVERFLOW

RCU

Receiver overflow. This bit is asserted when the flow control logic detects that the

transmitting device has illegally exceeded the number of credits that were issued.

16(1)

UNXP_CPL

RCU

Unexpected completion. This bit is asserted when a completion packet is received that

does not correspond to an issued request.

15(1)

CPL_ABORT

RCU

Completed abort. This bit is asserted when the bridge signals a completed abort.

14(1)

CPL_TIMEOUT

RCU

Completion time-out. This bit is asserted when no completion has been received for an

issued request before the time-out period.

13(1)

FC_ERROR

RCU

Flow control error. This bit is asserted when a flow control protocol error is detected either

during initialization or during normal operation.

12(1)

PSN_TLP

RCU

Poisoned TLP. This bit is asserted when a poisoned TLP is received.

11:5

RSVD

Reserved. Returns 000 0000b when read.

4(1)

DLL_ERROR

RCU

Data link protocol error. This bit is asserted if a data link layer protocol error is detected.

3:0

RSVD

Reserved. Returns 0h when read.

(1)

These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

PCIe Extended Configuration Space

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