XIO2221 datasheet(59/196 Pages) TI1

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XIO2221

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SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

4.27 Capabilities Pointer Register

This read-only register provides a pointer into the PCI configuration header where the PCI power

management block resides. Since the PCI power-management registers begin at 50h, this register is

hardwired to 50h.

PCI register offset:

34h

Read only

Default value:

50h

BIT NUMBER

RESET STATE

4.28 Interrupt Line Register

This read/write register is programmed by the system and indicates to the software which interrupt line the

bridge has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not

yet been assigned to the function. Since the bridge does not generate interrupts internally, this register is

a scratchpad register.

PCI register offset:

3Ch

Read/Write

Default value:

FFh

BIT NUMBER

RESET STATE

4.29 Interrupt Pin Register

The interrupt pin register is read-only 00h indicating that the bridge does not generate internal interrupts.

While the bridge does not generate internal interrupts, it does forward interrupts from the secondary

interface to the primary interface.

PCI register offset:

3Dh

Read only

Default value:

00h

BIT NUMBER

RESET STATE

Classic PCI Configuration Space

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