XIO2221 datasheet(67/196 Pages) TI1

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XIO2221

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SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

4.40 MSI Message Lower Address Register

This register contains the lower 32 bits of the address that a MSI message writes to when a serial IRQ is

detected. See Table 4-23 for a complete description of the register contents.

PCI register offset:

64h

Read only, Read/Write

Default value:

0000 0000h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 4-23. MSI Message Lower Address Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:2

ADDRESS

System specified message address

1:0

RSVD

Reserved. Returns 00b when read.

NOTE

Enabling MSI messaging in the XIO2221 has no effect.

4.41 MSI Message Upper Address Register

This register contains the upper 32 bits of the address that a MSI message writes to when a serial IRQ is

detected. If this register contains 0000 0000h, 32-bit addressing is used; otherwise, 64-bit addressing is

used.

PCI register offset:

68h

Read/Write

Default value:

0000 0000h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

NOTE

Enabling MSI messaging in the XIO2221 has no effect.

Classic PCI Configuration Space

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