XIO2221 datasheet(80/196 Pages) TI1

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XIO2221

SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

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4.61 GPIO Data Register

This register reads the state of the input-mode GPIO terminals and changes the state of the output-mode

GPIO terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The

secondary functions share GPIO4 (SCL) and GPIO5 (SDA). The default value at power up depends on

the state of the GPIO terminals as they default to general-purpose inputs. See Table 4-35 for a complete

description of the register contents.

PCI register offset:

B6h

Read only, Read/Write

Default value:

00XXh

BIT NUMBER

RESET STATE

Table 4-35. GPIO Data Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:8

RSVD

Reserved

7(1)

GPIO7_DATA

GPIO 7 data. This bit reads the state of GPIO7 when in input mode or changes the state of

GPIO7 when in output mode.

6(1)

GPIO6_DATA

GPIO 6 data. This bit reads the state of GPIO6 when in input mode or changes the state of

GPIO6 when in output mode.

5(1)

GPIO5_DATA

GPIO 5 data. This bit reads the state of GPIO5 when in input mode or changes the state of

GPIO5 when in output mode.

4(1)

GPIO4_DATA

GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of

GPIO4 when in output mode.

3(1)

GPIO3_DATA

GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of

GPIO3 when in output mode.

2(1)

GPIO2_DATA

GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of

GPIO2 when in output mode.

1(1)

GPIO1_DATA

GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of

GPIO1 when in output mode.

0(1)

GPIO0_DATA

GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of

GPIO0 when in output mode.

(1)

These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

Classic PCI Configuration Space

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