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XIO2221 Datasheet(PDF) 96 Page - Texas Instruments |
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XIO2221 Datasheet(HTML) 96 Page - Texas Instruments |
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96 / 196 page  XIO2221 SCPS216A – JULY 2009 – REVISED FEBRAURY 2010 www.ti.com 5.5 Uncorrectable Error Severity Register The uncorrectable error severity register controls the reporting of individual errors as ERR_FATAL or ERR_NONFATAL. When a bit is set, the corresponding error condition is identified as fatal. When a bit is cleared, the corresponding error condition is identified as nonfatal. See Table 5-4 for a complete description of the register contents. PCIe extended register offset: 10Ch Register type: Read only, Read/Write Default value: 0006 2011h BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 1 Table 5-4. Uncorrectable Error Severity Register Description BIT FIELD NAME ACCESS DESCRIPTION 31:21 RSVD R Reserved. Returns 000 0000 0000b when read. 20(1) UR_ERROR_SEVRO RW Unsupported request error severity 0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL. 19(1) ECRC_ERROR_SEVRR RW Extended CRC error severity 0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL. 18(1) MAL_TLP_SEVR RW Malformed TLP severity 0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL. 17(1) RX_OVERFLOW_SEVR RW Receiver overflow severity 0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL. 16(1) UNXP_CPL_SEVRP RW Unexpected completion severity 0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL. 15(1) CPL_ABORT_SEVR RW Completed abort severity 0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL. 14(1) CPL_TIMEOUT_SEVR RW Completion time-out severity 0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL. 13(1) FC_ERROR_SEVR RW Flow control error severity 0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL. 12(1) PSN_TLP_SEVR RW Poisoned TLP severity 0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL. 11:6 RSVD R Reserved. Returns 000 000b when read. 5 RSVD R Reserved. Returns 1h when read. 4(1) DLL_ERROR_SEVR RW Data link protocol error severity 0 = Error condition is signaled using ERR_NONFATAL. 1 = Error condition is signaled using ERR_FATAL. 3:1 RSVD R Reserved. Returns 000b when read. (1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted. 96 PCIe Extended Configuration Space Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): XIO2221 |
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