XIO2221 datasheet(74/196 Pages) TI1

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XIO2221

SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

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4.53 Link Capabilities Register

The link capabilities register indicates the link-specific capabilities of the bridge. See Table 4-29 for a

complete description of the register contents.

PCI register offset:

9Ch

Read only

Default value:

0006 XC11h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 4-29. Link Capabilities Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:24

PORT_NUM

Port number. This field indicates port number for the PCIe link. This field is read-only 00h

indicating that the link is associated with port 0.

23:19

RSVD

Reserved. Return 00 0000b when read.

CLK_PM

Clock power management. This bit is hardwired to 1 to indicate that XIO2221 supports clock

power management through CLKREQ protocol.

17:15

L1_LATENCY

L1 exit latency. This field indicates the time that it takes to transition from the L1 state to the L0

state. Bit 6 (CCC) in the link control register (offset A0h, see Section 4.54) equals 1b for a

common clock and equals 0b for an asynchronous clock.

For a common reference clock, the value of this field is determined by bits 20:18

(L1_EXIT_LAT_ASYNC) of the control and diagnostic register 1 (offset C4h, see Section 4.63).

For an asynchronous reference clock, the value of this field is determined by bits 17:15

(L1_EXIT_LAT_COMMON) of the control and diagnostic register 1 (offset C4h, see

Section 4.63).

14:12

L0S_LATENCY

L0s exit latency. This field indicates the time that it takes to transition from the L0s state to the

L0 state. Bit 6 (CCC) in the link control register (offset A0h, see Section 4.54) equals 1b for a

common clock and equals 0b for an asynchronous clock.

For a common reference clock, the value of 011b indicates that the L1 exit latency falls between

256 ns to less than 512 ns.

For an asynchronous reference clock, the value of 100b indicates that the L1 exit latency falls

between 512 ns to less than 1 s.

11:10

ASLPMS

Active-state link PM support. This field indicates the level of active-state power management

that the bridge supports. The value 11b indicates support for both L0s and L1 through

active-state power management.

9:4

MLW

Maximum link width. This field is encoded 00 0001b to indicate that the bridge only supports a

1× PCIe link.

3:0

MLS

Maximum link speed. This field is encoded 1h to indicate that the bridge supports a maximum

link speed of 2.5 Gb/s.

Classic PCI Configuration Space

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