XIO2221 datasheet(9/196 Pages) TI1

9 / 196 page

XIO2221

www.ti.com

SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

List of Tables

2-1

12 × 12 Terminals Sorted By Ball Number

.................................................................................... 17

2-2

12 × 12 Terminals Sorted Alphanumerically

.................................................................................. 19

2-3

Power-Supply Terminals

........................................................................................................ 22

2-4

Ground Terminals

................................................................................................................ 23

2-5

PCIe Terminals

................................................................................................................... 23

2-6

Clock Terminals

.................................................................................................................. 23

2-7

1394 Terminals

................................................................................................................... 24

2-8

Reserved Terminals

.............................................................................................................. 25

2-9

Miscellaneous Terminals

........................................................................................................ 26

3-1

XIO2221 Reset Options

......................................................................................................... 31

3-2

Initial Flow Control Credit Advertisements

.................................................................................... 32

3-3

Messages Supported by Bridge

................................................................................................ 33

3-4

EEPROM Register Loading Map

............................................................................................... 38

3-5

Registers Used To Program Serial-Bus Devices

............................................................................. 40

3-6

Clocking In Low Power States

.................................................................................................. 41

3-7

1394b OHCI Configuration Register Map

..................................................................................... 43

3-8

1394 OHCI Memory Command Options

...................................................................................... 44

4-1

Classic PCI Configuration Register Map

...................................................................................... 45

4-2

Command Register Description

............................................................................................... 47

4-3

Status Register Description

.................................................................................................... 48

4-4

Class Code and Revision ID Register Description

.......................................................................... 49

4-5

Device Control Base Address Register Description

........................................................................ 50

4-6

Device Control Base Address Register Description

........................................................................ 51

4-7

I/O Base Register Description

................................................................................................. 52

4-8

I/O Limit Register Description

.................................................................................................. 53

4-9

Secondary Status Register Description

...................................................................................... 54

4-10

Memory Base Register Description

........................................................................................... 55

4-11

Memory Limit Register Description

............................................................................................ 55

4-12

Prefetchable Memory Base Register Description

........................................................................... 56

4-13

Prefetchable Memory Limit Register Description

............................................................................ 56

4-14

Prefetchable Base Upper 32 Bits Register Description

.................................................................... 57

4-15

Prefetchable Limit Upper 32 Bits Register Description

..................................................................... 57

4-16

I/O Base Upper 16 Bits Register Description

................................................................................ 58

4-17

I/O Limit Upper 16 Bits Register Description

................................................................................ 58

4-18

Bridge Control Register Description

........................................................................................... 60

4-19

Power Management Capabilities Register Description

..................................................................... 63

4-20

Power Management Control/Status Register Description

.................................................................. 64

4-21

PM Bridge Support Extension Register Description

........................................................................ 65

4-22

MSI Message Control Register Description

.................................................................................. 66

4-23

MSI Message Lower Address Register Description

........................................................................ 67

4-24

MSI Message Data Register Description

..................................................................................... 68

4-25

PCI Express Capabilities Register Description

.............................................................................. 70

4-26

Device Capabilities Register Description

..................................................................................... 71

4-27

Device Control Register Description

.......................................................................................... 72

4-28

Device Status Register Description

........................................................................................... 73

4-29

Link Capabilities Register Description

........................................................................................ 74

List of Tables

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