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XIO2221 Datasheet(PDF) 72 Page - Texas Instruments |
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XIO2221 Datasheet(HTML) 72 Page - Texas Instruments |
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72 / 196 page  XIO2221 SCPS216A – JULY 2009 – REVISED FEBRAURY 2010 www.ti.com 4.51 Device Control Register The device control register controls PCIe device-specific meters. See Table 4-27 for a complete description of the register contents. PCI register offset: 98h Register type: Read only, Read/Write Default value: 2800h BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET STATE 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 Table 4-27. Device Control Register Description BIT FIELD NAME ACCESS DESCRIPTION 15 CFG_RTRY_ENB RW Configuration retry status enable. When this read/write bit is set to 1b, the bridge returns a completion with completion retry status on PCIe if a configuration transaction forwarded to the secondary interface did not complete within the implementation specific time-out period. When this bit is set to 0b, the bridge does not generate completions with completion retry status on behalf of configuration transactions. The default value of this bit is 0b. 14:12 MRRS RW Maximum read request size. This field is programmed by host software to set the maximum size of a read request that the bridge can generate. The bridge uses this field in conjunction with the cache line size register (offset 0Ch, see Section 7.6) to determine how much data to fetch on a read request. This field is encoded as: 000 = 128B 001 = 256B 010 = 512B (default) 011 = 1024B 100 = 2048B 101 = 4096B 110 = Reserved 111 = Reserved 11 ENS RW Enable no snoop. Controls the setting of the no snoop flag within the TLP header for upstream memory transactions mapped to any traffic class mapped to a virtual channel (VC) other than VC0 through the upstream decode windows. 0 = No snoop field is 0b. 1 = No snoop field is 1b (default). 10* APPE RW Auxiliary power PM enable. This bit has no effect in the bridge. 0 = AUX power is disabled (default). 1 = AUX power is enabled. 9 PFE R Phantom function enable. Since the bridge does not support phantom functions, this bit is read-only 0b. 8 ETFE R Extended tag field enable. Since the bridge does not support extended tags, this bit is read-only 0b. 7:5 MPS RW Maximum payload size. This field is programmed by host software to set the maximum size of posted writes or read completions that the bridge can initiate. This field is encoded as: 000 = 128B (default) 001 = 256B 010 = 512B 011 = 1024B 100 = 2048B 101 = 4096B 110 = Reserved 111 = Reserved 4 ERO R Enable relaxed ordering. Since the bridge does not support relaxed ordering, this bit is read-only 0b. 3 URRE RW Unsupported request reporting enable. If this bit is set, the bridge sends an ERR_NONFATAL message to the root complex when an unsupported request is received. 0 = Do not report unsupported requests to the root complex (default) 1 = Report unsupported requests to the root complex 72 Classic PCI Configuration Space Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): XIO2221 |
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