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XIO2221 Datasheet(PDF) 11 Page - Texas Instruments |
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XIO2221 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 196 page  XIO2221 www.ti.com SCPS216A – JULY 2009 – REVISED FEBRAURY 2010 7-18 Link Enhancement Control Register Description .......................................................................... 126 7-19 Subsystem Access Register Description ................................................................................... 127 8-1 OHCI Register Map ............................................................................................................. 128 8-2 OHCI Version Register Description .......................................................................................... 131 8-3 GUID ROM Register Description ............................................................................................ 132 8-4 Asynchronous Transmit Retries Register Description ..................................................................... 133 8-5 CSR Control Register Description ........................................................................................... 134 8-6 Configuration ROM Header Register Description .......................................................................... 135 8-7 Bus Options Register Description ............................................................................................ 136 8-8 Configuration ROM Mapping Register Description ........................................................................ 138 8-9 Posted Write Address Low Register Description .......................................................................... 138 8-10 Posted Write Address High Register Description .......................................................................... 139 8-11 Host Controller Control Register Description ............................................................................... 141 8-12 Self-ID Count Register Description .......................................................................................... 142 8-13 Isochronous Receive Channel Mask High Register Description ......................................................... 143 8-14 Isochronous Receive Channel Mask Low Register Description ......................................................... 145 8-15 Interrupt Event Register Description ......................................................................................... 146 8-16 Interrupt Mask Register Description ......................................................................................... 147 8-17 Isochronous Transmit Interrupt Event Register Description .............................................................. 150 8-18 Isochronous Receive Interrupt Event Register Description ............................................................... 151 8-19 Initial Bandwidth Available Register Description ........................................................................... 152 8-20 Initial Channels Available High Register Description ...................................................................... 153 8-21 Initial Channels Available Low Register Description ...................................................................... 153 8-22 Fairness Control Registre Description ...................................................................................... 154 8-23 Link Control Register Description ............................................................................................ 155 8-24 Node Identification Register Description .................................................................................... 156 8-25 PHY Control Register Description ........................................................................................... 157 8-26 Isochronous Cycle Timer Register Description ............................................................................ 158 8-27 Asynchronous Request Filter High Register Description ................................................................. 159 8-28 Asynchronous Request Filter Low Register Description .................................................................. 161 8-29 Physical Request Filter High Register Description ........................................................................ 162 8-30 Physical Request Filter Low Register Description ......................................................................... 164 8-31 Asynchronous Context Control Register Description ...................................................................... 165 8-32 Asynchronous Context Command Pointer Register Description ......................................................... 166 8-33 Isochronous Transmit Context Control Register Description ............................................................. 167 8-34 Isochronous Receive Context Control Register Description ............................................................. 169 8-35 Isochronous Receive Context Match Register Description ............................................................... 170 9-1 TI Extension Register Map .................................................................................................... 172 9-2 Isochronous Receive Digital Video Enhancement Registers Description .............................................. 173 9-3 Link Enhancement Control Registers Description ......................................................................... 174 9-4 Timestamp Offset Registers Description .................................................................................... 176 10-1 Base Register Description .................................................................................................... 178 10-2 Base Register Field Description .............................................................................................. 179 10-3 Page 0 (Port Status) Register Description .................................................................................. 181 10-4 Page 0 (Port Status) Register Field Description ........................................................................... 182 10-5 Page 1 (Vendor ID) Register Configuration ................................................................................ 183 10-6 Page 1 (Vendor ID) Register Field Descriptions ........................................................................... 184 10-7 Page 7 (Vendor Dependent) Register Configuration ...................................................................... 185 Copyright © 2009–2010, Texas Instruments Incorporated List of Tables 11 |
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