XIO2221 datasheet(90/196 Pages) TI1

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XIO2221

SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

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4.71 Arbiter Request Mask Register

The arbiter request mask register enables and disables support for requests from specific masters on the

secondary bus. The arbiter request mask register also controls if a request input is automatically masked

on an arbiter time-out. See Table 4-42 for a complete description of the register contents.

PCI register offset:

DDh

Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

Table 4-42. Arbiter Request Mask Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7(1)

ARB_TIMEOUT

Arbiter time-out. This bit enables the arbiter time-out feature. The arbiter time-out is

defined as the number of PCI clocks after the PCI bus has gone idle for a device to assert

FRAME before the arbiter assumes the device will not respond.

0 = Arbiter time disabled (default)

1 = Arbiter time-out set to 16 PCI clocks

6(1)

AUTO_MASK

Automatic request mask. This bit enables automatic request masking when an arbiter

time-out occurs.

0 = Automatic request masking disabled (default)

1 = Automatic request masking enabled

5:1(1)

RSVD

Reserved. These bits are reserved and must not be changed from their default value of

00000b.

0(1)

REQ0_MASK

Request 0 (REQ0) mask. Setting this bit forces the internal arbiter to ignore requests

signal on request input 0.

0 = Use 1394a OHCI request (default)

1 = Ignore 1394a OHCI request

(1)

These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.

Classic PCI Configuration Space

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