XIO2221 datasheet(82/196 Pages) TI1

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XIO2221

SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

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Table 4-36. Control and Diagnostic Register 0 Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

6(1)

PREFETCH_4X

Prefetch 4× enable

0 = Bridge prefetches up to two cache lines, as defined in the cache line size

transactions (default).

1 = Bridge prefetches up to four cache lines, as defined in the cache line size

transactions.

Note: When this bit is set and the FORCE_MRM bit in the general control register is

set, both upstream memory read multiple transactions and upstream memory

transactions prefetch up to four cache lines.

Note: When the READ_PREFETCH_DIS bit in the general control register is set, this bit

has no effect and only one DWORD will be fetched on a burst read.

This bit only affects the XIO2221 design when the EN_CACHE_LINE_CHECK bit is set.

5:4(1)

UP_REQ_BUF_VALUE

PCI upstream req-res buffer threshold value. The value in this field controls the buffer

space that must be available for the device to accept a PCI bus transaction. If the

cache line size is not valid, the device will use eight DW for calculating the threshold

value.

00 = 1 cache line + 4 DW (default)

01 = 1 cache line + 8 DW

10 = 1 cache line + 12 DW

11 = 2 cache lines + 4 DW

3(1)

UP_REQ_BUF_CTRL

PCI upstream req-res buffer threshold control. This bit enables the PCI upstream

req-res buffer threshold control mode of the bridge.

0 = PCI upstream req-res buffer threshold control mode disabled (default)

1 = PCI upstream req-res buffer threshold control mode enabled

2(1)

CFG_ACCESS_MEM_RE

Configuration access to memory-mapped registers. When this bit is set, the bridge

allows configuration access to memory-mapped configuration registers.

1(1)

RSVD

Reserved. Bit 1 defaults to 0b. If this register is programmed via EEPROM or another

mechanism, the value written into this field must be 0b.

RSVD

Reserved. Returns 0b when read.

Classic PCI Configuration Space

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