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XIO2221

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SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

4.54 Link Control Register

The link control register controls link-specific behavior. See Table 4-30 for a complete description of the

PCI register offset:

A0h

Read only, Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

Table 4-30. Link Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:9

RSVD

Reserved. Returns 00h when read.

CPM_EN

Clock power management enable. This bit is used to enable XIO2221 to use CLKREQ for

clock power management

0 = Clock power management is disabled and XIO2221 shall hold the CLKREQ

signal low.

1 = Clock power management is enabled and XIO2221 is permitted to use the

CLKREQ signal to allow the REFCLK input to be stopped.

Extended synch. This bit forces the bridge to extend the transmission of FTS ordered sets

and an extra TS2 when exiting from L1 prior to entering to L0.

0 = Normal synch (default)

1 = Extended synch

CCC

Common clock configuration. When this bit is set, it indicates that the bridge and the

device at the opposite end of the link are operating with a common clock source. A value

of 0b indicates that the bridge and the device at the opposite end of the link are operating

with se te reference clock sources. The bridge uses this common clock configuration

information to report the correct L0s and L1 exit latencies.

0 = Reference clock is asynchronous (default).

1 = Reference clock is common.

Retrain link. This bit has no function and is read-only 0b.

Link disable. This bit has no function and is read-only 0b.

RCB

Read completion boundary. This bit is an indication of the RCB of the root complex. The

state of this bit has no effect on the bridge, since the RCB of the bridge is fixed at 128

bytes.

0 = 64 bytes (default)

1 = 128 bytes

RSVD

Reserved. Returns 0b when read.

1:0

ASLPMC

Active-state link PM control. This field enables and disables the active-state PM.

00 = Active-state PM disabled (default)

01 = L0s entry enabled

10 = L1 entry enabled

11 = L0s and L1 entry enabled

Classic PCI Configuration Space

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