XIO2221 datasheet(28/196 Pages) TI1

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PCIExpress

Transmitter

PCIExpress

Receiver

PCIBusInterface

Configurationand

MemoryRegister

GPIO

Serial

EEPROM

Reset

Controller

Clock

Generator

Power

Mgmt

1394bOHCIwith1-PortPHY

1394CablePort

XIO2221

SCPS216A – JULY 2009 – REVISED FEBRAURY 2010

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Feature/Protocol Descriptions

This chapter provides a high-level overview of all significant device features. Figure 3-1 shows a simplified

block diagram of the basic architecture of the PCIe to PCI bridge with 1394b OHCI and 1-port PHY. The

top of the diagram is the PCIe interface, and the 1394b OHCI with 1-port PHY is located at the bottom of

the diagram.

Figure 3-1. XIO2221 Block Diagram

3.1

Power-Up/Power-Down Sequencing

The bridge contains both 1.5-V and 3.3-V power terminals. The following power-up and power-down

sequences describe how power is applied to these terminals.

In addition, the bridge has three resets: PERST, GRST, and an internal power-on reset. These resets are

described in Section 3.2. The following power-up and power-down sequences describe how PERST is

applied to the bridge.

The application of the PCIe reference clock (REFCLK) is important to the power-up/-down sequence and

is included in the following power-up and power-down descriptions.

Feature/Protocol Descriptions

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XIO2221 Datasheet(PDF) 28 Page - Texas Instruments